Masayuki Ito

22 papers A* 3B 1C 2Journal 6Unranked 10
YearRankTypeTitle / Venue / Authors
2023 — conf
Architecture Challenges for Heterogeneous Processors in Embedded SoCs.
A-SSCC
Masayuki Ito
2020 — conf
Architecture and Interface for Collaborating with a Group of Agents in an Adversarial Game.
IIAI-AAI
Natsuki Matsunami, Masayuki Ito, Sotaro Karakama
2018 A* conf
A Single-Planner Approach to Multi-Modal Humanoid Mobility.
ICRA
Andrew Dornbush, Karthik Vijayakumar, Sameer Bardapurkar, Fahad Islam, Masayuki Ito, Maxim Likhachev
2017 — conf
3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV.
ISSCC
Hayato Kimura, Hideyuki Noda, Hisaaki Watanabe, Takashi Higuchi, Ryosaku Kobayashi, Masayuki Utsuno, Fumitake Takami, Sugako Otani, Masayuki Ito, Yasuhisa Shimazaki, Naoki Yada, Hiroyuki Kondo
2013 — conf
Compact ROSA for 100-Gb/s (4 × 25 Gb/s) Ethernet with a PLC-based AWG demultiplexer.
OFC/NFOEC
Yoshiyuki Doi, Manabu Oguma, Masayuki Ito, Ikuo Ogawa, Toshihide Yoshimatsu, Tetsuichiro Ohno, Eiji Yoshida, Hiroshi Takahashi
2011 J jnl
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.
IEICE Trans. Electron.
Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima
2010 — conf
A 45nm 37.3GOPS/W heterogeneous multi-core SoC.
ISSCC
Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima
2009 J jnl
A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU.
IEEE J. Solid State Circuits
Masayuki Ito, Kenichi Nitta, Koji Ohno, Masahito Saigusa, Masaki Nishida, Shinichi Yoshioka, Takahiro Irita, Takao Koike, Tatsuya Kamei, Teruyoshi Komuro, Toshihiro Hattori, Yasuhiro Arai, Yukio Kodama
2009 — conf
A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management.
ASP-DAC
Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka
2009 J jnl
Domain Partitioning Technology for Embedded Multicore Processors.
IEEE Micro
Tohru Nojiri, Yuki Kondo, Naohiko Irie, Masayuki Ito, Hajime Sasaki, Hideo Maejima
2009 B conf
Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme.
ICPP
Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara
2008 — conf
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.
ISSCC
Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara
2008 A* conf
Bari-bari-II: Jack-up rescue robot with debris opening function.
ICRA
Hideyuki Tsukagoshi, Ato Kitagawa, Masayuki Ito, Kuniaki Ooe, Ichiro Kiryu, T. Kochiya
2007 — conf
A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS.
ISSCC
Masayuki Ito, Toshihiro Hattori, Takahiro Irita, Ken Tatezawa, Fumihito Tanaka, Kenji Hirose, Shinichi Yoshioka, Koji Ohno, Reiko Tsuchihashi, Minoru Sakata, Masayuki Yamamoto, Yuji Aral
2006 — conf
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor.
ISSCC
Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno
2006 A* conf
Hierarchical power distribution and power management scheme for a single chip mobile processor.
DAC
Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno
2006 — conf
SH-MobileG1: A single-chip application and dual-mode baseband processor.
Hot Chips Symposium
Masayuki Ito, Takahiro Irita, Eiji Yamamoto, Kunihiko Nishiyama, Takao Koike, Yoshihiko Tsuchihashi, Hiroyuki Asano, Hiroshi Yagi, Saneaki Tamaki, Ken Tatezawa, Toshihiro Hattori, Shinichi Yoshioka, Koji Ohno
2003 C conf
Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition.
ICCD
Masayuki Ito, David G. Chinnery, Kurt Keutzer
1997 J jnl
Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification.
IEEE Trans. Computers
Masayuki Ito, Naofumi Takagi, Shuzo Yajima
1996 J jnl
Square Rooting by Iterative Multiply-Additions.
Inf. Process. Lett.
Masayuki Ito, Naofumi Takagi, Shuzo Yajima
1995 C conf
Efficient Initial Approximation and Fast Converging Methods for Division and Square Root.
IEEE Symposium on Computer Arithmetic
Masayuki Ito, Naofumi Takagi, Shuzo Yajima
1990 J jnl
Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nagisa Ishiura, Masayuki Ito, Shuzo Yajima