Masayoshi Yoshimura

39 papers C 14Journal 7Unranked 18

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Multiple Target Seed Generation Method for Random Pattern Resistant Faults on Built-In Self-Test. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takanobu Sone, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai
2025	—	`conf`	A Don't Care Filling Method for Control Signals on State Transitions of Controllers to Minimize the Estimated Number of Test Patterns for Data-Paths. ATS Haruta Tokuta, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai
2025	—	`conf`	PBO-Based Pattern Replacement for Compacting Diagnostic Patterns to Achieve Complete Diagnostic Resolution. DFT Tatsuya Aono, Toshinori Hosokawa, Masayoshi Yoshimura, Koji Yamazaki, Masayuki Arai
2024	—	`conf`	A Low Power Oriented Multiple Target Test Generation Method for 2-Cycle Gate-Exhaustive Faults. DFT Toshinori Hosokawa, Momona Mizota, Masayoshi Yoshimura, Masayuki Arai
2024	J	`jnl`	CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayoshi Yoshimura, Atsuya Tsujikawa, Toshinori Hosokawa
2023	—	`conf`	A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage. DFT Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai
2023	—	`conf`	An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing. DFT Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa, Masayoshi Yoshimura
2023	—	`conf`	An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers. DFT Toshinori Hosokawa, Kyohei Iizuka, Masayoshi Yoshimura
2022	—	`conf`	CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level. DFT Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, Toshinori Hosokawa
2020	C	`conf`	A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method. IOLTS Toshinori Hosokawa, Kenichiro Misawa, Hiroshi Yamazaki, Masayoshi Yoshimura, Masayuki Arai
2020	—	`conf`	A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT. DFT Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai
2019	C	`conf`	A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths. IOLTS Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura
2019	—	`conf`	A Low Capture Power Oriented X-filling Method Using Partial MaxSAT Iteratively. DFT Toshinori Hosokawa, Hiroshi Yamazaki, Kenichiro Misawa, Masayoshi Yoshimura, Yuki Hirama, Masavuki Arai
2019	—	`conf`	A State Assignment Method to Improve Transition Fault Coverage for Controllers. DFT Masayoshi Yoshimura, Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa
2019	C	`conf`	An Efficient SAT-Attack Algorithm Against Logic Encryption. IOLTS Yusuke Matsunaga, Masayoshi Yoshimura
2018	C	`conf`	A Capture Safe Static Test Compaction Method Based on Don't Cares. IOLTS Sayuri Ochi, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura
2018	C	`conf`	A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification. IOLTS Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume
2018	C	`conf`	A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns. IOLTS Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura
2017	J	`jnl`	A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa
2017	C	`conf`	A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations. PRDC Masayoshi Yoshimura, Tomohiro Bouyashiki, Toshinori Hosokawa
2017	C	`conf`	Controller augmentation and test point insertion at RTL for concurrent operational unit testing. IOLTS Toshinori Hosokawa, Shun Takeda, Hiroshi Yamazaki, Masayoshi Yoshimura
2015	—	`conf`	A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions. ATS Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa
2013	J	`jnl`	A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution. IEICE Trans. Inf. Syst. Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura
2013	C	`conf`	A don't care identification method for test compaction. DDECS Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura
2013	—	`conf`	A smart Trojan circuit and smart attack method in AES encryption circuits. DFTS Masayoshi Yoshimura, Amy Ogita, Toshinori Hosokawa
2013	J	`jnl`	Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga
2012	J	`jnl`	An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. Inf. Media Technol. Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
2012	J	`jnl`	An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
2012	C	`conf`	Methodology for early estimation of hierarchical routing resources in 3D FPGAs. VLSI-SoC Krishna Chaitanya Nunna, Farhad Mehdipour, Masayoshi Yoshimura, Kazuaki J. Murakami
2012	C	`conf`	Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	—	`conf`	A Soft Error Tolerance Estimation Method for Sequential Circuits. DFT Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
2011	C	`conf`	Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010	C	`conf`	Evaluation of transition untestable faults using a multi-cycle capture test generation method. DDECS Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki
2006	—	`conf`	Development of practical ATPG tool with flexible interface. ATS Masayoshi Yoshimura, Yusuke Matsunaga
2005	—	`conf`	Implementation of Multiobjective Optimization Procedures at the Product Design Planning Stage. System Modelling and Optimization Masayoshi Yoshimura
2004	C	`conf`	SemanticObjects and Biomedical Informatics. BIBE Atsushi Kitazawa, Masayoshi Yoshimura
2002	—	`conf`	A Test Point Insertion Method to Reduce the Number of Test Patterns. Asian Test Symposium Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta
2002	—	`conf`	Collaborative optimization for product design and manufacturing. CAD Masayoshi Yoshimura
2001	—	`conf`	Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. ASP-DAC Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta