Masayoshi Tachibana

13 papers C 2Journal 7Unranked 4
YearRankTypeTitle / Venue / Authors
2018 J jnl
Phase difference analysis technique for parametric faults BIST in CMOS analog circuits.
IEICE Electron. Express
Chatchai Wannaboon, Nattagit Jiteurtragool, Wimol San-Um, Masayoshi Tachibana
2018 J jnl
Robustification of a One-Dimensional Generic Sigmoidal Chaotic Map with Application of True Random Bit Generation.
Entropy
Nattagit Jiteurtragool, Masayoshi Tachibana, Wimol San-Um
2017 J jnl
A simple current-reversible chaotic jerk circuit using inherent tanh(x) of an opamp.
IEICE Electron. Express
Patinya Ketthong, Wimol San-Um, Banlue Srisuchinwong, Masayoshi Tachibana
2015 — conf
An autonomous chaotic oscillator based on hyperbolic tangent nonlinearity.
ISCIT
Chatchai Wannaboon, Masayoshi Tachibana
2015 — conf
True Random Number Generator based on compact chaotic oscillator.
ISCIT
Nattagit Jiteurtragool, Chatchai Wannaboon, Masayoshi Tachibana
2013 J jnl
A resistance matching based self-testable current-mode R-2R digital-to-analog converter.
IEICE Electron. Express
Jun Yuan, Masayoshi Tachibana
2012 J jnl
A common-mode BIST technique for fully-differential sample-and-hold circuits.
IEICE Electron. Express
Jun Yuan, Masayoshi Tachibana
2011 — conf
A BIST scheme for operational amplifier by checking the stable output of transient response.
ECCTD
Jun Yuan, Masayoshi Tachibana
2010 J jnl
A Fault Signature Characterization Based Analog Circuit Testing Scheme and the Extension of IEEE 1149.4 Standard.
IEICE Trans. Inf. Syst.
Wimol San-Um, Masayoshi Tachibana
2010 C conf
A low-jitter supply-regulated charge pump phase-locked loop with built-in test and calibration.
ISCAS
Wimol San-Um, Masayoshi Tachibana
2009 — conf
Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits.
SBCCI
Wimol San-Um, Masayoshi Tachibana
1989 C conf
High performance I/O processors for real-time pulse handling.
ICCD
Masayoshi Tachibana, Yoshihisa Kondo, Yasuo Yamada, Masafumi Takahashi, Haruyuki Tago
1986 J jnl
A Hardware Maze Router with Application to Interactive Rip-Up and Reroute.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki