Masaya Yoshikawa

105 papers A 1B 1C 14Misc 9Journal 11Unranked 69

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Parameter Free Countermeasure Against Adversarial Examples. ICCAE Takumi Tojo, Ryo Kumagai, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
2025	—	`conf`	Power Based Side-Channel Analysis for Lightweight Cipher Ltlbc. ICCAE Yusuke Nozaki, Shu Takemoto, Masaya Yoshikawa
2025	—	`conf`	Quantitative Evaluation of Vulnerabilities in Adversarial Shadow Attack. ICCAE Chisei Ishida, Ryo Kumagai, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
2025	—	`conf`	Quantization of Tiny MLP-Mixer and Its Evaluation. ICCAE Ryo Kumagai, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
2025	—	`conf`	Security Evaluation of Differentially Private Federated Learning Against Model Inversion Attacks. ICCAE Kohei Kanada, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
2024	—	`conf`	Adversarial Examples for Field Programmable Gate Array based AI Module. AICCC Yusuke Nozaki, Shu Takemoto, Masaya Yoshikawa
2024	—	`conf`	Error Correction Method for Lightweight Cipher PRINCE based Physically Unclonable Function. ITCC Yusuke Nozaki, Shu Takemoto, Masaya Yoshikawa
2024	—	`conf`	Hue and Saturation oriented Imperceptible Adversarial Examples and their Evaluation. ITCC Ryo Kumagai, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
2024	—	`conf`	Luminance Correction based Countermeasure against Adversarial Examples. ITCC Takumi Tojo, Ryo Kumagai, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
2024	—	`conf`	SuperSonic Glitch Physical Unclonable Function for Encryption and Device Authentication. AICCC Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
2023	—	`conf`	Deep Learning Based Side-Channel Analysis for Lightweight Cipher PRESENT. ICCAE Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa
2023	—	`conf`	Explainable AI based Adversarial Examples and its Evaluation. ICECC Ryo Kumagai, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
2023	—	`conf`	Hamming Weight aware Fault Analysis for Lightweight Cryptography TWINE. CCIOT Yusuke Nozaki, Shu Takemoto, Masaya Yoshikawa
2023	—	`conf`	Implementation and Evaluation of the Lightweight Cipher SPARKLE. ICECC Masato Sato, Yusuke Nozaki, Masaya Yoshikawa
2023	—	`conf`	Machine Learning Based Power Analysis for Simon with Secure Mechanism. ICCAE Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa
2023	—	`conf`	Security Evaluation of Glitch Based Authentication Function for Edge AI. GCCE Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa
2023	—	`conf`	Tamper Resistance Evaluation of Midori128 against Differential Power Analysis. ICKII Yusuke Nozaki, Shu Takemoto, Masaya Yoshikawa
2022	—	`conf`	AI Hardware Oriented Trojan Detection Architecture. ICECC Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa
2022	—	`conf`	Authenticated Encryption based Secure In-vehicle System against DoS Attacks. GCCE Daichi Hirose, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
2021	—	`conf`	Hardware Trojan for Lightweight Cryptoraphy Elephant. GCCE Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa
2021	—	`conf`	Neural Network Based Glitch Physically Unclonable Function. UEMCON Yusuke Nozaki, Masaya Yoshikawa
2021	—	`conf`	Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7. ISDCS Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa
2020	—	`conf`	Tamper Resistance Evaluation of TWINE Implemented on 8-bit Microcontroller. ICSIM Yusuke Nozaki, Masaya Yoshikawa
2020	Misc	`conf`	Unrolled PRINCE Cipher based Glitch Physically Unclonable Function. ICISS Yusuke Nozaki, Masaya Yoshikawa
2019	A	`conf`	Countermeasure of Lightweight Physical Unclonable Function Against Side-Channel Attack. CCC Yusuke Nozaki, Masaya Yoshikawa
2019	—	`conf`	Evaluation of the Hiding-Countermeasure PRINCE Using Differential Power Analysis. GCCE Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
2019	—	`conf`	Performance Evaluation of CAESAR Authenticated Encryption on SROS2. AICCC Shu Takemoto, Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa, Shinya Honda, Ryo Kurachi
2019	—	`conf`	Quantitative Performance Evaluation of PL PUF and RO PUF with ASIC Implementation. GCCE Yusuke Nozaki, Masaya Yoshikawa
2019	—	`conf`	Scalability and Performance Evaluation of GA Based Modeling Analysis for RO PUF. GCCE Taichi Umeda, Yusuke Nozaki, Masaya Yoshikawa
2019	—	`conf`	Secret Sharing Schemes Based Secure Authentication for Physical Unclonable Function. ICCCS Yusuke Nozaki, Masaya Yoshikawa
2019	—	`conf`	Security Evaluation of Counter Synchronization Method for CAN Against DoS Attack. GCCE Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa
2019	—	`conf`	Security Evaluation of Ring Oscillator PUF Against Genetic Algorithm Based Modeling Attack. IMIS Yusuke Nozaki, Masaya Yoshikawa
2019	—	`conf`	Side-Channel Analysis for Searchable Encryption System and its Security Evaluation. CSE/EUC Masaya Yoshikawa, Yusuke Nozaki
2019	—	`conf`	Side-Channel Resistance Evaluation Method using Statistical Tests for Physical Unclonable Function. ICAIIC Yusuke Nozaki, Masaya Yoshikawa
2019	C	`conf`	Statistical Power Analysis for IoT Device Oriented Encryption with Glitch Canceller. IWCIA Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
2018	—	`conf`	EM based machine learning attack for XOR arbiter PUF. ICMLSC Yusuke Nozaki, Masaya Yoshikawa
2018	—	`conf`	Feasibility Evaluation of Neural Network Physical Unclonable Function. GCCE Kazuya Shibagaki, Taichi Umeda, Yusuke Nozaki, Masaya Yoshikawa
2018	—	`conf`	Feature Extraction Driven Modeling Attack Against Double Arbiter PUF and Its Evaluation. AICCC Susumu Matsumi, Yusuke Nozaki, Masaya Yoshikawa
2018	—	`conf`	Implementation of Searchable Encryption System with Dedicated Hardware and its Evaluation. UEMCON Masaya Yoshikawa, Yoshiya Ikezaki, Yusuke Nozaki
2018	—	`conf`	Lethal Genes Aware Genetic Programming Analysis for RO PUF. GCCE Taichi Umeda, Kazuya Shibagaki, Yusuke Nozaki, Masaya Yoshikawa
2018	—	`conf`	Lightweight Cipher Aware Countermeasure Using Random Number Masks and Its Evaluation. ICVISP Masaya Yoshikawa, Yusuke Nozaki
2018	—	`conf`	Security Evaluation of a Lightweight Cipher SPECK against Round Addition DFA. AICCC Yusuke Nozaki, Masaya Yoshikawa
2018	—	`conf`	Shuffling Based Side-Channel Countermeasure for Energy Harvester. GCCE Yusuke Nozaki, Masaya Yoshikawa
2017	—	`conf`	Electromagnetic analysis method for ultra low power cipher Midori. UEMCON Masaya Yoshikawa, Yusuke Nozaki
2017	—	`conf`	FPGA implementation technique for power consumption aware tamper resistance accelerator of lightweight PUF. GCCE Yoshiya Ikezaki, Yusuke Nozaki, Hideki Nagata, Masaya Yoshikawa
2017	—	`conf`	Helper Data Aware Cloning Method for Physical Unclonable Function. SmartCloud Masaya Yoshikawa, Yusuke Nozaki
2017	—	`conf`	Hierarchical power analysis attack for falsification detection cipher. CCWC Masaya Yoshikawa, Yusuke Nozaki
2017	—	`conf`	Power analysis for a lightweight authenticated encryption SIMON-JAMBU. GCCE Yusuke Nozaki, Yoshiya Ikezaki, Hideki Nagata, Masaya Yoshikawa
2017	—	`conf`	Statistical fault analysis for a lightweight cipher midori. ICIA Yusuke Nozaki, Masaya Yoshikawa
2017	—	`conf`	Tamper resistance evaluation of PUF implementation against machine learning attack. ICBEA Yusuke Nozaki, Masaya Yoshikawa
2016	—	`conf`	Deep learning attack for physical unclonable function. GCCE Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa
2016	—	`conf`	Hardware Trojan for an authenticated encryption Minalpher. GCCE Yusuke Nozaki, Yoshiya Ikezaki, Masaya Yoshikawa
2016	—	`conf`	Multiple Rounds Aware Power Analysis Attack for a Lightweight Cipher SIMECK. BigDataService Masaya Yoshikawa, Yusuke Nozaki, Kensaku Asahi
2016	—	`conf`	Two Stage Fault Analysis against a Falsification Detection Cipher Minalpher. SmartCloud Masaya Yoshikawa, Yusuke Nozaki
2016	—	`conf`	Vulnerability Evaluation Accelerator for Lightweight Ciphers. BigDataSecurity/HPSC/IDS Masaya Yoshikawa, Yusuke Nozaki, Kensaku Asahi
2015	C	`conf`	Design and LSI prototyping of security module with hardware trojan. ICCE Masaya Yoshikawa, Takuya Tsukadaira, Takeshi Kumaki
2015	—	`conf`	Detection technique for hardware Trojans using machine learning in frequency domain. GCCE Takato Iwase, Yusuke Nozaki, Masaya Yoshikawa, Takeshi Kumaki
2015	—	`conf`	Frequency Domain Aware Power Analysis Attack against Random Clock LSI for Secure Automotive Embedded Systems. VTC Fall Masaya Yoshikawa, Yusuke Nozaki, Toshiya Asai, Kensaku Asahi
2015	—	`conf`	Hardware Trojan for ultra lightweight block cipher Piccolo. GCCE Kohei Nohara, Yusuke Nozaki, Masaya Yoshikawa
2015	C	`conf`	Power analysis for clock fluctuation LSI. SNPD Yusuke Nozaki, Toshiya Asai, Kensaku Asahi, Masaya Yoshikawa
2015	J	`jnl`	Secure in-vehicle Systems using Authentication. Int. J. Networked Distributed Comput. Masaya Yoshikawa, Kyota Sugioka, Yusuke Nozaki, Kensaku Asahi
2015	C	`conf`	Secure in-vehicle systems against Trojan attacks. ICIS Masaya Yoshikawa, Kyota Sugioka, Yusuke Nozaki, Kensaku Asahi
2015	—	`conf`	Statistical fault analysis for a lightweight block cipher TWINE. GCCE Yusuke Nozaki, Kensaku Asahi, Masaya Yoshikawa
2014	C	`conf`	Error value driven fault analysis attack. SNPD Masaya Yoshikawa, Hikaru Goto, Kensaku Asahi
2014	—	`conf`	PUF ID generation method for modeling attacks. GCCE Yusuke Nozaki, Kensaku Asahi, Masaya Yoshikawa
2014	J	`jnl`	Security Evaluation of RG-DTM PUF Using Machine Learning Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mitsuru Shiozaki, Kousuke Ogawa, Kota Furuhashi, Takahiko Murayama, Masaya Yoshikawa, Takeshi Fujino
2014	—	`conf`	Study of threat for automotive embedded system by Trojan virus. GCCE Kohei Nohara, Kensaku Asahi, Masaya Yoshikawa
2014	C	`conf`	Vulnerability evaluation of multiplexing PUF for SVM attacks. ICSEng S. Kiryu, Kensaku Asahi, Masaya Yoshikawa
2013	—	`conf`	Cipher-destroying and secret-key-emitting hardware Trojan against AES core. MWSCAS Takeshi Kumaki, Masaya Yoshikawa, Takeshi Fujino
2013	C	`conf`	Hardware Trojan for security LSI. ICCE Masaya Yoshikawa, R. Satoh, Takeshi Kumaki
2013	—	`conf`	Platform for Verification of Electromagnetic Analysis Attacks against Cryptographic Circuits. ITNG Masaya Yoshikawa, Toshiya Asai
2013	—	`conf`	The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3. VLSI-DAT Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino
2012	J	`jnl`	High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications. IEICE Trans. Electron. Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino
2012	J	`jnl`	Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka, Masaya Yoshikawa, Takeshi Fujino
2012	Misc	`conf`	Multiplexing aware arbiter physical unclonable function. IRI Masaya Yoshikawa, Akira Naruse
2012	J	`jnl`	Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino
2011	—	`conf`	A power grid optimization algorithm considering via reliability. ECCTD Masahiro Fukui, Haruo Miki, Masaya Yoshikawa, Shuji Tsukiyama
2011	C	`conf`	Efficient Random Number for the Masking Method against DPA Attacks. ICSEng Masaya Yoshikawa, Y. Kojima
2011	Misc	`conf`	Multi-rounds masking method against DPA attacks. IRI Masaya Yoshikawa, M. Sugiyama
2011	J	`jnl`	Placement Tool Dedicated for a Via-Programmable Logic Device VPEX. Int. J. Comput. Their Appl. Masaya Yoshikawa, Takeshi Fujino
2010	Misc	`conf`	Hybrid Ant Colony Optimization for intensification and diversification. IRI Masaya Yoshikawa, Shimohigashi Yoshiaki
2010	C	`conf`	Placement Tool Dedicated for a Via-programmable Logic Device VPEX. CAINE Masaya Yoshikawa, Yuichi Kokusyo, Takeshi Fujino
2009	Misc	`conf`	Adaptive Immune Algorithm Considering Intensification and Diversification. IRI Masaya Yoshikawa, Akira Naruse, Shinsuke Souboku
2009	C	`conf`	An Efficient Hardware Accelerator for Power Grid Simulation. ISCAS Taiki Hashizume, Hisako Sugano, Shinichi Nishizawa, Masaya Yoshikawa, Masahiro Fukui
2009	—	`conf`	Car Navigation System Based on Hybrid Genetic Algorithm. CSIE (5) Masaya Yoshikawa, Hidekazu Terai
2009	—	`conf`	Dedicated Hardware for Ant Colony Optimization Using Distributed Memory. ITNG Masaya Yoshikawa, Hidekazu Terai
2009	—	`conf`	OX Hardware Engine for High Speed Character Inheritance. GEM Masaya Yoshikawa, Hidekazu Terai
2008	—	`conf`	Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization. GEM Masaya Yoshikawa, Hidekazu Terai
2008	J	`jnl`	Hybrid Architecture of Genetic Algorithm and Simulated Annealing. Eng. Lett. Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Terai
2008	J	`jnl`	Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing. IEICE Trans. Electron. Akihiro Nakamura, Masahide Kawarasaki, Kouta Ishibashi, Masaya Yoshikawa, Takeshi Fujino
2008	Misc	`conf`	Route selection algorithm based on integer operation Ant Colony Optimization. IRI Masaya Yoshikawa, Hidekazu Terai
2007	Misc	`conf`	Architecture for high-speed Ant Colony Optimization. IRI Masaya Yoshikawa, Hidekazu Terai
2007	—	`conf`	Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing. CICC Akihiro Nakamura, Masahide Kawaharazaki, Masaya Yoshikawa, Takeshi Fujino
2007	J	`jnl`	Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption. J. Adv. Comput. Intell. Intell. Informatics Masaya Yoshikawa, Hidekazu Terai
2007	J	`jnl`	The new DFM approach based on a genetic algorithm. Artif. Life Robotics Masaya Yoshikawa, Hidekazu Terai
2006	C	`conf`	Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing. SERA Masaya Yoshikawa, Hidekazu Terai
2006	C	`conf`	Co-evolutionary robotics using two kinds of neural networks. CAINE Masaya Yoshikawa, Hidekazu Terai
2006	J	`jnl`	Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation. J. Adv. Comput. Intell. Intell. Informatics Masaya Yoshikawa, Hidekazu Terai
2006	Misc	`conf`	Immune Algorithm Processor. CATA Masaya Yoshikawa, Masahiro Fukui, Hidekazu Terai
2005	C	`conf`	A Hierarchical Parallel Placement Technique based on Genetic Algorithm. ISDA Masaya Yoshikawa, Hidekazu Terai
2005	C	`conf`	Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique. SERA Masaya Yoshikawa, Hidekazu Terai
2005	—	`conf`	Hybrid genetic algorithm engine for high-speed floorplanning. ECCTD Masaya Yoshikawa, Hidekazu Terai
2005	B	`conf`	Performance driven placement technique based on collaboration of software and hardware. Congress on Evolutionary Computation Masaya Yoshikawa, Hidekazu Terai
2004	—	`conf`	VLSI processor architecture for real-time GA processing and PE-VLSI design. ISCAS (3) Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi
2002	Misc	`conf`	Scalable GA processor architecture and its implementation of processor-element. ICASSP Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi