Masaya Miyahara

80 papers C 2Journal 41Unranked 37
YearRankTypeTitle / Venue / Authors
2026 — conf
A 500kGy Radiation-Hardened 2.4GHz Wi-Fi Receiver for Innovative Nuclear Power Plant Decommissioning.
ISSCC
Yasuto Narukiyo, Sena Kato, Kotaro Yanaka, Yuya Takahashi, Masaya Miyahara, Jill C. Mayeda, Atsushi Shirane
2023 J jnl
A Quick Startup Low-Power Hybrid Crystal Oscillator for IoT Applications.
IEICE Trans. Electron.
Masaya Miyahara, Zule Xu, Takehito Ishii, Noritoshi Kimura
2021 J jnl
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth.
IEEE J. Solid State Circuits
Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Jian Pang, Hanli Liu, Masaya Miyahara, Atsushi Shirane, Kenichi Okada
2019 J jnl
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance.
IEEE J. Solid State Circuits
Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Atsushi Shirane, Kenichi Okada
2019 — conf
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment.
A-SSCC
Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto
2019 J jnl
Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector.
IEICE Trans. Electron.
Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2018 J jnl
A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS.
IEEE J. Solid State Circuits
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2018 — conf
A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier.
VLSI Circuits
Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira Matsuzawa
2018 J jnl
A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells.
IEICE Trans. Electron.
Tohru Kaneko, Yuya Kimura, Masaya Miyahara, Akira Matsuzawa
2018 J jnl
A 7GS/s Complete-DDFS-Solution in 65nm CMOS.
IEICE Trans. Electron.
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2018 J jnl
SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier.
IEICE Electron. Express
Akira Matsuzawa, Masaya Miyahara
2017 — conf
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.
ISSCC
Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2017 J jnl
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay.
IEEE J. Solid State Circuits
Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2017 — conf
A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS.
ESSCIRC
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2017 J jnl
A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input.
IEICE Trans. Electron.
Tohru Kaneko, Yuya Kimura, Masaya Miyahara, Akira Matsuzawa
2017 — conf
A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS.
A-SSCC
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2017 — conf
An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier.
CICC
Masaya Miyahara, Akira Matsuzawa
2017 J jnl
High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator.
IEICE Trans. Electron.
Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa
2017 — conf
SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier.
ASICON
Akira Matsuzawa, Masaya Miyahara
2017 — conf
Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network.
ASICON
Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016 — conf
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay.
ISSCC
Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016 J jnl
A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture.
IEICE Trans. Electron.
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2016 — conf
A 2
A-SSCC
Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2016 — conf
A 2 GHz 3.1 mW type-I digital ring-based PLL.
ESSCIRC
Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016 J jnl
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture.
IEEE J. Solid State Circuits
Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016 J jnl
A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC.
IEEE J. Solid State Circuits
Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016 C conf
A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC.
ISCAS
Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa
2016 — conf
A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter.
ESSCIRC
Tohru Kaneko, Yuya Kimura, Koji Hirose, Masaya Miyahara, Akira Matsuzawa
2016 J jnl
A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers.
IEEE J. Solid State Circuits
Lilan Yu, Masaya Miyahara, Akira Matsuzawa
2016 — conf
A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers.
A-SSCC
Lilan Yu, Masaya Miyahara, Akira Matsuzawa
2016 J jnl
A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC.
IEICE Trans. Electron.
Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2016 J jnl
A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yu Hou, Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2016 — conf
A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder.
ESSCIRC
Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2016 — conf
An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation.
A-SSCC
Rui Wu, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016 J jnl
Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC.
IEICE Trans. Electron.
Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2016 J jnl
Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques.
IEICE Trans. Electron.
Lilan Yu, Masaya Miyahara, Akira Matsuzawa
2016 J jnl
Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Mitsutoshi Sugawara, Kenji Mori, Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015 — conf
19.5 An HCI-healing 60GHz CMOS transceiver.
ISSCC
Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015 — conf
25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture.
ISSCC
Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015 — conf
A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise.
A-SSCC
Zule Xu, Masaya Miyahara, Akira Matsuzawa
2015 — conf
A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers.
A-SSCC
Lilan Yu, Masaya Miyahara, Akira Matsuzawa
2015 — conf
A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC.
VLSIC
Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2015 J jnl
A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency.
IEICE Trans. Electron.
Tohru Kaneko, Masaya Miyahara, Akira Matsuzawa
2015 — conf
A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture.
ASICON
Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2015 J jnl
An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yu Hou, Takamoto Watanabe, Masaya Miyahara, Akira Matsuzawa
2015 J jnl
An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers.
IEEE J. Solid State Circuits
James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
2015 J jnl
Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
2015 J jnl
Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product.
IEEE Trans. Very Large Scale Integr. Syst.
James Lin, Ibuki Mano, Masaya Miyahara, Akira Matsuzawa
2014 — conf
20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding.
ISSCC
Kenichi Okada, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Rui Wu, Masaya Miyahara, Akira Matsuzawa
2014 — conf
22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers.
ISSCC
Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada, Akira Matsuzawa
2014 — conf
A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier.
A-SSCC
James Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa
2014 J jnl
A 7-bit 1-GS/s Flash ADC with Background Calibration.
IEICE Trans. Electron.
Sanroku Tsukamoto, Masaya Miyahara, Akira Matsuzawa
2014 J jnl
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration.
IEEE J. Solid State Circuits
Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2014 — conf
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation.
ASP-DAC
Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2014 — conf
All-digital 0.016mm
ICECS
Takamoto Watanabe, Yu Hou, Masaya Miyahara, Akira Matsuzawa
2014 J jnl
An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
James Lin, Masaya Miyahara, Akira Matsuzawa
2014 J jnl
Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator.
IEICE Trans. Electron.
Jeonghoon Han, Masaya Miyahara, Akira Matsuzawa
2014 — conf
Radio receiver front-end using time-based all-digital ADC (TAD).
ICECS
Tomohito Terasawa, Yuji Kamiya, Hiroyuki Kawashima, Kenichiro Imai, Masanobu Suzuki, Takamoto Watanabe, Nobuyuki Taguchi, Manabu Sawada, Yu Hou, Yoshiyuki Hirooka, Hong Phuc Ninh, Masaya Miyahara, Akira Matsuzawa
2013 — conf
A 0.022mm
ISSCC
Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2013 — conf
A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers.
CICC
James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
2013 — conf
A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC.
CICC
Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
2013 — conf
A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS.
NEWCAS
Zule Xu, Masaya Miyahara, Akira Matsuzawa
2013 J jnl
A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hyunui Lee, Masaya Miyahara, Akira Matsuzawa
2013 — conf
A 12-bit interpolated pipeline ADC using body voltage controlled amplifier.
NEWCAS
Hyunui Lee, Masaya Miyahara, Akira Matsuzawa
2013 J jnl
A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hyunui Lee, Yusuke Asada, Masaya Miyahara, Akira Matsuzawa
2013 J jnl
A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs.
IEICE Trans. Electron.
Fei Li, Masaya Miyahara, Akira Matsuzawa
2013 J jnl
A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells.
IEICE Trans. Electron.
Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa
2013 J jnl
Design of CMOS Low-Noise Analog Circuits for Particle Detector Pixel Readout LSIs.
IEICE Trans. Electron.
Fei Li, Masaya Miyahara, Akira Matsuzawa
2013 J jnl
Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers.
IEICE Trans. Electron.
Hyunui Lee, Masaya Miyahara, Akira Matsuzawa
2013 J jnl
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry.
IEEE J. Solid State Circuits
Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa
2012 J jnl
A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching.
IEICE Trans. Electron.
Hong Phuc Ninh, Masaya Miyahara, Akira Matsuzawa
2012 — conf
A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry.
ISSCC
Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa
2012 J jnl
An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Daehwa Paik, Masaya Miyahara, Akira Matsuzawa
2011 C conf
A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique.
ISCAS
James Lin, Masaya Miyahara, Akira Matsuzawa
2011 — conf
A time-domain architecture and design method of high speed A-to-D converters with standard cells.
A-SSCC
Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa
2011 — conf
An analysis on a pseudo-differential dynamic comparator with load capacitance calibration.
ASICON
Daehwa Paik, Masaya Miyahara, Akira Matsuzawa
2010 J jnl
An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Daehwa Paik, Yusuke Asada, Masaya Miyahara, Akira Matsuzawa
2009 — conf
Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof.
ICECS
Kaziiya Kojima, Yasuhiro Toriyama, Toru Taniguchi, Masaya Miyahara, Akira Matsuzawa
2008 J jnl
A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masaya Miyahara, Akira Matsuzawa
2007 J jnl
The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time.
IEICE Trans. Electron.
Masaya Miyahara, Akira Matsuzawa