Masaya Kibune

34 papers Journal 17Unranked 17
YearRankTypeTitle / Venue / Authors
2017 — conf
Efficient Learning Algorithm Using Compact Data Representation in Neural Networks.
ICONIP (2)
Masaya Kibune, Michael G. Lee
2015 — conf
22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI.
ISSCC
Yanfei Chen, Masaya Kibune, Asako Toda, Akinori Hayakawa, Tomoyuki Akiyama, Shigeaki Sekiguchi, Hiroji Ebe, Nobuhiro Imaizumi, Tomoyuki Akahoshi, Suguru Akiyama, Shinsuke Tanaka, Takasi Simoyama, Ken Morito, Takuji Yamamoto, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
2015 — conf
A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects.
OFC
Akinori Hayakawa, Masaya Kibune, Asako Toda, Shinsuke Tanaka, Takasi Simoyama, Yanfei Chen, Tomoyuki Akiyama, Shigekazu Okumura, Takeshi Baba, Tomoyuki Akahoshi, Seiji Ueno, Kazunori Maruyama, Masahiko Imai, Jian Hong Jiang, Pradip Thachile, Tamer Riad, Shigeaki Sekiguchi, Suguru Akiyama, Yu Tanaka, Ken Morito, Daisuke Mizutani, Toshihiko Mori, Takuji Yamamoto, Hiroji Ebe
2015 J jnl
A 3x blind ADC-based CDR for a 20 dB loss channel.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2015 J jnl
A Reference-Less Single-Loop Half-Rate Binary CDR.
IEEE J. Solid State Circuits
Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2015 J jnl
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs.
IEEE J. Solid State Circuits
Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2014 — conf
A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE.
CICC
Clifford Ting, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2014 J jnl
An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset".
IEEE Trans. Circuits Syst. I Regul. Pap.
Ravi Shivnaraine, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2014 — conf
On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs.
VLSIC
Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013 J jnl
A Blind Baud-Rate ADC-Based CDR.
IEEE J. Solid State Circuits
Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013 — conf
A blind baud-rate ADC-based CDR.
ISSCC
Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013 — conf
An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection.
CICC
Mohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2011 — conf
A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS.
ISSCC
Behrooz Abiri, Ravi Shivnaraine, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2011 — conf
A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS.
ISSCC
Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2011 — conf
A pattern-guided adaptive equalizer in 65nm CMOS.
ISSCC
Shayan Shahramian, Clifford Ting, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2011 J jnl
An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS.
IEEE J. Solid State Circuits
Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2010 J jnl
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
IEEE J. Solid State Circuits
Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker
2010 J jnl
A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS.
IEEE J. Solid State Circuits
Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa
2010 — conf
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.
ISSCC
Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh
2010 J jnl
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
2010 — conf
A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.
CICC
Tina Tahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune
2010 — conf
A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS.
ISSCC
Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto
2010 J jnl
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.
IEICE Trans. Electron.
Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2009 J jnl
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.
IEEE J. Solid State Circuits
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2009 — conf
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.
ISSCC
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2009 — conf
Split capacitor DAC mismatch calibration in successive approximation ADC.
CICC
Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2008 — conf
A dynamic offset control technique for comparator design in scaled CMOS technology.
CICC
Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
2007 J jnl
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS.
IEEE J. Solid State Circuits
Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
2006 — conf
A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid.
ISSCC
Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
2006 J jnl
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies.
IEICE Trans. Electron.
Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa
2005 J jnl
A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS.
IEEE J. Solid State Circuits
Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda
2005 J jnl
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique.
IEEE J. Solid State Circuits
Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda
2005 J jnl
A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization.
IEEE J. Solid State Circuits
Hirohito Higashi, Syunitirou Masaki, Masaya Kibune, Satoshi Matsubara, Takaya Chiba, Yoshiyasu Doi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Hirotaka Tamura
2003 J jnl
A CMOS multichannel 10-Gb/s transceiver.
IEEE J. Solid State Circuits
Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura