Masatoshi Arai

11 papers B 1C 1Misc 1Journal 4Unranked 4
YearRankTypeTitle / Venue / Authors
2023 J jnl
RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability.
IEICE Trans. Inf. Syst.
Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
2022 — conf
RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA.
HEART
Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
2022 J jnl
Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA.
Int. J. Netw. Comput.
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
2021 J jnl
CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis.
IEICE Trans. Inf. Syst.
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
2021 — conf
Weight Least Square Filter for Improving the Quality of Depth Map on FPGA.
CANDAR (Workshops)
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
2020 — conf
CLAHE implementation on a low-end FPGA board by high-level synthesis.
CANDAR (Workshops)
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
2011 — conf
Face Image Enhancement Taking into Account Lighting Behavior on a Face.
CAIP (2)
Masato Tsukada, Chisato Funayama, Masatoshi Arai, Charles Dubout
2010 J jnl
Ultra-High-Speed Image Signal Accumulation Sensor.
Sensors
Takeharu Goji Etoh, Son Dao Vu Truong, Toshiaki Koike-Akino, Toshiro Akino, Kenji Nishi, Masatoshi Kureta, Masatoshi Arai
2007 B conf
A High Speed License Plate Recognition System on an FPGA.
FPL
Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka
2007 C conf
Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA.
CIT
Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka
1993 Misc conf
A neural inverse function for automatic test pattern generation using strictly digital neural networks.
VTS
Masatoshi Arai, Tohru Nakagawa, Hajime Kitagawa