Masato Motomura

149 papers A* 4A 4B 7C 9Misc 6Journal 62Unranked 56

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	AQPIM: Breaking the PIM Capacity Wall for LLMs with in-Memory Activation Quantization. HPCA Kosuke Matsushima, Yasuyuki Okoshi, Masato Motomura, Daichi Fujiki
2026	J	`jnl`	Memory-Efficient and Trustworthy Neural Networks via Random Seed-Based Design. IEEE Access Hiroaki Ito, Hikari Otsuka, Ryota Yasudo, Zhiqiang Que, José Gabriel F. Coutinho, Daichi Fujiki, Masato Motomura, Ce Guo, Wayne Luk
2026	A*	`conf`	The Strong Lottery Ticket Hypothesis for Multi-Head Attention Mechanisms. AAAI Hikari Otsuka, Daiki Chijiwa, Yasuyuki Okoshi, Daichi Fujiki, Susumu Takeuchi, Masato Motomura
2025	J	`jnl`	A Flip-Count-Based Dynamic Temperature Control Method for Constrained Combinatorial Optimization by Parallel Annealing Algorithms. IEICE Trans. Inf. Syst. Genta Inoue, Daiki Okonogi, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2025	J	`jnl`	Amorphica: A Fully Connected Annealer Supporting Metamorphic Annealing and Scalable Multi Chip Integration. IEEE Access Daiki Okonogi, Jaehoon Yu, Satoru Jimbo, Genta Inoue, Akira Hyodo, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2025	J	`jnl`	Annealed Mean Field Descent Is Highly Effective for Quadratic Unconstrained Binary Optimization. CoRR Kyo Kuroki, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2025	J	`jnl`	Binary Quadratic Quantization: Beyond First-Order Quantization for Real-Valued Matrix Compression. CoRR Kyo Kuroki, Yasuyuki Okoshi, Thiem Van Chu, Kazushi Kawamura, Masato Motomura
2025	A*	`conf`	BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT. ISCA Jiale Yan, Hiroaki Ito, Yuta Nagahara, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki
2025	J	`jnl`	DMSA: An Efficient Architecture for Sparse-Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow. IEEE Trans. Very Large Scale Integr. Syst. Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Daichi Fujiki, Masato Motomura, Thiem Van Chu
2025	J	`jnl`	Derek Chiou. IEEE Micro Doug Burger, Paul Chow, Joel S. Emer, Mark D. Hill, James C. Hoe, Masato Motomura
2025	J	`jnl`	Partially Frozen Random Networks Contain Compact Strong Lottery Tickets. Trans. Mach. Learn. Res. Hikari Otsuka, Daiki Chijiwa, Ángel López García-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura
2025	J	`jnl`	Rethinking Optimal Verification Granularity for Compute-Efficient Test-Time Scaling. CoRR Hao Mark Chen, Guanxi Lu, Yasuyuki Okoshi, Zhiwen Mo, Masato Motomura, Hongxiang Fan
2025	—	`conf`	TTF-GNN: Memory-Efficient GNNs via Tensor Train Decomposition and Network Folding. COOL CHIPS Hiroaki Ito, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki
2025	J	`jnl`	The Strong Lottery Ticket Hypothesis for Multi-Head Attention Mechanisms. CoRR Hikari Otsuka, Daiki Chijiwa, Yasuyuki Okoshi, Daichi Fujiki, Susumu Takeuchi, Masato Motomura
2025	J	`jnl`	TicketLLM: Next-Generation Sparse and Low-bit Transformers with Supermask-based Method. Trans. Mach. Learn. Res. Yasuyuki Okoshi, Hikari Otsuka, Daichi Fujiki, Masato Motomura
2025	—	`conf`	Trustworthy Deep Learning Acceleration with Customizable Design Flow Automation. HEART Zhiqiang Que, Hongxiang Fan, Gabriel F. Figueiredo, Ce Guo, Wayne Luk, Ryota Yasudo, Masato Motomura
2025	J	`jnl`	Uncovering Strong Lottery Tickets in Graph Transformers: A Path to Memory Efficient and Robust Graph Learning. Trans. Mach. Learn. Res. Hiroaki Ito, Jiale Yan, Hikari Otsuka, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki
2025	J	`jnl`	WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration. IEEE Access Ángel López García-Arias, Yasuyuki Okoshi, Jaehoon Yu, Junnosuke Suzuki, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura
2024	J	`jnl`	A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization. IEEE Access Satoru Jimbo, Tatsuhiko Shirai, Nozomu Togawa, Masato Motomura, Kazushi Kawamura
2024	—	`conf`	A Parallel-Trial Double-Update Annealing Processor for Enabling Highly-Effective Solution Search of Constrained Combinatorial Optimization Problems. ICFPT Akira Hyodo, Satoru Jimbo, Daiki Okonogi, Genta Inoue, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2024	C	`conf`	An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection. ICCE Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2024	A	`conf`	Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization. GECCO Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2024	B	`conf`	ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data. IJCNN Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
2024	C	`conf`	Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA. ICCE Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
2024	J	`jnl`	Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching. IEEE Access Yuki Ichikawa, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
2024	—	`conf`	Exploiting N:M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization. CANDAR Akihiro Shioda, Ángel López García-Arias, Hikari Otsuka, Yuki Ichikawa, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura
2024	C	`conf`	Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA. ICCE Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
2024	C	`conf`	High Throughput Datapath Design for Vision Permutator FPGA Accelerator. ICCE Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2024	J	`jnl`	Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket. CoRR Hikari Otsuka, Daiki Chijiwa, Ángel López García-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura
2024	J	`jnl`	Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. IEEE Access Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2024	—	`conf`	Progressive Variable Precision DNN With Bitwise Ternary Accumulation. AICAS Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2024	—	`conf`	RAW 2024 Invited Talk-5. IPDPS (Workshops) Masato Motomura
2024	J	`jnl`	Restricted Random Pruning at Initialization for High Compression Range. Trans. Mach. Learn. Res. Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura
2024	B	`conf`	Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow. ASPDAC Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
2024	J	`jnl`	Toward Improving Ensemble-Based Collaborative Inference at the Edge. IEEE Access Shungo Kumazawa, Jaehoon Yu, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2024	—	`conf`	WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression. A-SSCC Yasuyuki Okoshi, Ángel López García-Arias, Jaehoon Yu, Junnosuke Suzuki, Hikari Otsuka, Thiem Van Chu, Kazushi Kawamura, Daichi Fujiki, Masato Motomura
2023	J	`jnl`	A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems. IEICE Trans. Inf. Syst. Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
2023	—	`conf`	A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. MCSoC Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura
2023	—	`conf`	Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. ISSCC Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura
2023	Misc	`conf`	Decision Forest Training Accelerator Based on Binary Feature Decomposition. FCCM Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
2023	—	`conf`	Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance. COOL CHIPS Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
2023	—	`conf`	Multicoated and Folded Graph Neural Networks With Strong Lottery Tickets. LoG Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2023	J	`jnl`	Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets. CoRR Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2023	—	`conf`	Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. VLSI Technology and Circuits Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2023	J	`jnl`	Recurrent Residual Networks Contain Stronger Lottery Tickets. IEEE Access Ángel López García-Arias, Yasuyuki Okoshi, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
2023	J	`jnl`	TT-MLP: Tensor Train Decomposition on Deep MLPs. IEEE Access Jiale Yan, Kota Ando, Jaehoon Yu, Masato Motomura
2022	J	`jnl`	A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers. IEICE Trans. Inf. Syst. Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
2022	—	`conf`	APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control. IPDPS Workshops Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
2022	—	`conf`	Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. ISSCC Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura
2022	A*	`conf`	Multicoated Supermasks Enhance Hidden Networks. ICML Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2022	J	`jnl`	Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark. IEEE Trans. Circuits Syst. Video Technol. Yafei Ou, Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
2022	—	`conf`	Ring-VCO-based ReLU activation function with linearity improvement for pulsed neuron circuits. ICECS 2022 Pitchayapatchaya Srikram, Prasoon Ambalathankandy, Yuri Kanazawa, Masato Motomura, Masayuki Ikebe
2021	J	`jnl`	A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
2021	—	`conf`	A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning. FPT Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
2021	—	`conf`	Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. HCS Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2021	J	`jnl`	ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training. Int. J. Netw. Comput. Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2021	A	`conf`	Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. BMVC Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
2021	J	`jnl`	Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. CoRR Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
2021	J	`jnl`	ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. Int. J. Netw. Comput. Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2021	J	`jnl`	STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
2021	J	`jnl`	Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture. IEEE Access Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, Masato Motomura
2020	—	`conf`	7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. ISSCC Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
2020	C	`conf`	A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. ISCAS Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
2020	J	`jnl`	A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. Int. J. Netw. Comput. Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda
2020	J	`jnl`	An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA. IEEE Trans. Circuits Syst. Video Technol. Prasoon Ambalathankandy, Masayuki Ikebe, Takayuki Yoshida, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai
2020	—	`conf`	ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training. CANDAR Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2020	—	`conf`	Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs. ARC Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki
2020	—	`conf`	ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. CANDAR Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2019	—	`conf`	A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators. CANDAR Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2019	—	`conf`	DeltaNet: Differential Binary Neural Network. ASAP Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2019	J	`jnl`	Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. IEICE Trans. Inf. Syst. Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2019	J	`jnl`	FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Trans. Inf. Syst. Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2019	J	`jnl`	Foreword. IEICE Trans. Inf. Syst. Masato Motomura
2019	J	`jnl`	Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Yohan Frans, Wim Dehaene, Masato Motomura, Seung-Jun Bae
2019	J	`jnl`	QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
2019	Misc	`conf`	Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. DICTA Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
2018	—	`ch.`	Advanced Devices and Architectures. Principles and Structures of FPGAs Masato Motomura, Masanori Hariyama, Minoru Watanabe
2018	C	`conf`	Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. VCIP Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
2018	—	`conf`	Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. MCSoC Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2018	J	`jnl`	BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
2018	—	`conf`	Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. FPT Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2018	—	`conf`	New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. VLSI Circuits Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura
2018	J	`jnl`	Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. Complex. Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
2018	—	`conf`	QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
2018	J	`jnl`	Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. Microprocess. Microsystems Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano
2018	—	`conf`	Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee. ISSCC Dejan Markovic, Masato Motomura, Byeong-Gyu Nam
2018	Misc	`conf`	Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. ICASSP Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai
2017	A	`conf`	A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). FPGA Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura
2017	—	`conf`	A Time-Division Multiplexing Ising Machine on FPGAs. HEART Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	—	`conf`	Accelerating deep learning by binarized hardware. APSIPA Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	—	`conf`	An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning. ARC Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura
2017	—	`conf`	An image sensor/processor 3D stacked module featuring ThruChip interfaces. ASP-DAC Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura
2017	J	`jnl`	Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation. IEEE Trans. Circuits Syst. II Express Briefs Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani
2017	B	`conf`	Exploring optimized accelerator design for binarized convolutional neural networks. IJCNN Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	—	`conf`	F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems. ISSCC Meng-Fan Chang, Jun Deguchi, Vivek De, Masato Motomura, Shinichiro Shiratake, Marian Verhelst
2017	B	`conf`	FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. FPL Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
2017	—	`conf`	In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	C	`conf`	Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. ISCAS Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
2017	—	`conf`	Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. CANDAR Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2017	—	`conf`	Low latency divider using ensemble of moving average curves. ISQED Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura
2017	—	`conf`	Quantization Error-Based Regularization in Neural Networks. SGAI Conf. Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2016	—	`conf`	A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors. APCCAS Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2016	—	`conf`	A memory-based realization of a binarized deep convolutional neural network. FPT Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura
2016	—	`conf`	An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions. ReConFig Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2016	—	`conf`	FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. ReConFig Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2016	—	`conf`	Foreword. VLSI Circuits Jeffrey C. Gealow, Masato Motomura
2016	J	`jnl`	Introduction to the Special Issue on the 2015 Symposium on VLSI Circuits. IEEE J. Solid State Circuits Masato Motomura, Andreia Cathelin
2016	C	`conf`	Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. ISCAS Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
2016	J	`jnl`	Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata. Int. J. Unconv. Comput. Miho Ushida, Alexandre Schmid, Tetsuya Asai, Kazuyoshi Ishimura, Masato Motomura
2016	—	`conf`	Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. ESSCIRC Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura
2015	J	`jnl`	Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation. IEEE Trans. Circuits Syst. II Express Briefs Kamal El-Sankary, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda
2015	J	`jnl`	Enhancing Memcached by Caching Its Data and Functionalities at Network Interface. J. Inf. Process. Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
2015	—	`conf`	Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. VLSIC Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
2015	J	`jnl`	Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits. IEEE J. Solid State Circuits Jeffrey C. Gealow, Masato Motomura
2015	J	`jnl`	Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration. IEICE Trans. Electron. Li-Chung Hsu, Masato Motomura, Yasuhiro Take, Tadahiro Kuroda
2014	—	`conf`	A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator. A-SSCC Itaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura
2014	—	`conf`	Achieving higher performance of memcached by caching at network interface. FPT Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
2014	B	`conf`	Caching memcached at reconfigurable network interface. FPL Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
2014	J	`jnl`	Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates. IEICE Electron. Express Lizeth Gonzalez-Carabarin, Tetsuya Asai, Masato Motomura
2013	—	`conf`	A restricted dynamically reconfigurable architecture for low power processors. ReConFig Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura
2013	—	`conf`	C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join. ARC Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura
2013	J	`jnl`	C-Based Complex Event Processing on Reconfigurable Hardware. IEEE Trans. Very Large Scale Integr. Syst. Hiroaki Inoue, Takashi Takenaka, Masato Motomura
2013	—	`conf`	Exploiting hardware reconfigurability on window join. HPCS Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Tetsuya Asai, Masato Motomura
2013	—	`conf`	Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. ICECS Katsuki Ohata, Yukitoshi Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda
2011	B	`conf`	20Gbps C-Based Complex Event Processing. FPL Hiroaki Inoue, Takashi Takenaka, Masato Motomura
2011	—	`conf`	Panel discussions: Impact on society by fusion and harmony of mobile devices, servers, and networks - Their direction of evolutions and optimal roles. COOL Chips Masato Motomura, Takafumi Aoki, Toru Awashima, Toru Baji, Masaaki Ishikawa
2011	—	`conf`	Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS. ISSCC Makoto Miyamura, Shogo Nakaya, Munehiro Tada, Toshitsugu Sakamoto, Koichiro Okamoto, Naoki Banno, Shinji Ishida, Kimihiko Ito, Hiromitsu Hada, Noboru Sakimura, Tadahiko Sugibayashi, Masato Motomura
2011	J	`jnl`	Test compression for dynamically reconfigurable processors. ACM Trans. Reconfigurable Technol. Syst. Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Masato Motomura, Koichiro Furuta
2004	J	`jnl`	A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems. IEEE Trans. Computers Mahmoud Méribout, Masato Motomura
2004	J	`jnl`	Efficient metrics and high-level synthesis for dynamically reconfigurable logic. IEEE Trans. Very Large Scale Integr. Syst. Mahmoud Méribout, Masato Motomura
2004	Misc	`conf`	Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. FCCM Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima
2004	—	`conf`	Stream applications on the dynamically reconfigurable processor. FPT Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima
2004	J	`jnl`	Wrapper-based bus implementation techniques for performance improvement and cost reduction. IEEE J. Solid State Circuits Kenichiro Anjo, Atsushi Okamura, Masato Motomura
2003	J	`jnl`	A Hierarchical Cost Estimation Technique for High Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mahmoud Méribout, Masato Motomura
2003	—	`conf`	A New Hardware Algorithm for Fast IP Routing Targeting Programmable Routers. Net-Con Mahmoud Méribout, Masato Motomura
2003	A	`conf`	A New Reconfigurable Hardware Architecture for High Throughput Networking Applications and its Design Methodology. IPDPS Mahmoud Méribout, Masato Motomura
2003	J	`jnl`	New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic. J. Syst. Archit. Mahmoud Méribout, Masato Motomura
2000	C	`conf`	A Study of Channeled DRAM Memory Architectures. ICCD Lars Friebe, Yoshikazu Yabe, Masato Motomura
2000	Misc	`conf`	A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. FCCM Yuichiro Shibata, Masaki Uno, Hideharu Amano, Koichiro Furuta, Taro Fujii, Masato Motomura
2000	—	`conf`	Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk. ASP-DAC Masakazu Yamashina, Masato Motomura
2000	—	`conf`	Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI. CICC Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina
1998	J	`jnl`	An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing. IEEE J. Solid State Circuits Hiroyuki Igura, Yukihiro Naito, Kenya Kazama, Ichiro Kuroda, Masato Motomura, Masakazu Yamashina
1998	Misc	`conf`	An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration. FCCM Masato Motomura, Yoshiharu Aimoto, Atsufkni Shibayama, Yoshikazu Yabe, Masakazu Yamashina
1995	J	`jnl`	Cache-processor coupling: a fast and wide on-chip data cache design. IEEE J. Solid State Circuits Masato Motomura, Toshiaki Inoue, Hachiro Yamada, Akihiko Konagaya
1995	B	`conf`	Ordered multithreading: a novel technique for exploiting thread-level parallelism. PACT Masato Motomura, Toshiaki Inoue, Sunao Torii, Akihiko Konagaya
1994	J	`jnl`	A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. IEEE J. Solid State Circuits Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada
1993	J	`jnl`	A 300-MHz 16-b BiCMOS video signal processor. IEEE J. Solid State Circuits Toshiaki Inoue, Junichi Goto, Masakazu Yamashina, Kazumasa Suzuki, Masahiro Nomura, Youichi Koseki, Tohru Kimura, Takao Atsumo, Masato Motomura, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada, Masahide Takada
1992	J	`jnl`	A 2 K-word dictionary search processor (DISP) LSI with an approximate word search capability. IEEE J. Solid State Circuits Masato Motomura, Hachiro Yamada, Tadayoshi Enomoto
1990	J	`jnl`	A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM. IEEE J. Solid State Circuits Masato Motomura, Jun Toyoura, Kazumi Hirata, Hideyuki Ooka, Hachiro Yamada, Tadayoshi Enomoto