Masato Inagi

23 papers B 2C 4Journal 10Unranked 7
YearRankTypeTitle / Venue / Authors
2024 — conf
A Proposal of Equivalence Classes in Maximally Asymmetric Functions and Their Application to Benchmark Generation.
ISMVL
Rie Kometani, Shinobu Nagayama, Martin Lukac, Masato Inagi, Shin'ichi Wakabayashi
2023 J jnl
Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection.
IPSJ Trans. Syst. LSI Des. Methodol.
Gaku Kataoka, Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
2018 — conf
A Nearest Neighbor Search Engine Using Distance-Based Hashing.
FPT
Toshitaka Ito, Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
2018 — conf
An Approximate Nearest Neighbor Search Algorithm Using Distance-Based Hashing.
DEXA (2)
Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
2018 C conf
Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection.
DSD
Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
2016 — conf
An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data.
FPT
Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
2015 J jnl
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi
2014 J jnl
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating.
Inf. Media Technol.
Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
2014 J jnl
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating.
IPSJ Trans. Syst. LSI Des. Methodol.
Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
2014 — conf
An ILP-Based Optimal Circuit Mapping Method for PLDs.
IPDPS Workshops
Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko
2013 C conf
A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA.
DSD
Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi
2013 C conf
A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions.
DSD
Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
2012 J jnl
A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks.
IEICE Trans. Inf. Syst.
Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro
2011 B conf
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators.
FPL
Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama
2011 — conf
EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture.
ReConFig
Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro
2010 J jnl
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems.
Inf. Media Technol.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2010 J jnl
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems.
IPSJ Trans. Syst. LSI Des. Methodol.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2009 B conf
Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems.
FPL
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2008 C conf
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems.
ISCAS
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
2008 J jnl
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
2007 J jnl
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
2006 — conf
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os.
FPT
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
2002 J jnl
An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kengo R. Azegami, Masato Inagi, Atsushi Takahashi, Yoji Kajitani