Masashi Tawada

44 papers A 1C 11Misc 2Journal 16Unranked 14

Year	Rank	Type	Title / Venue / Authors
2026	C	`conf`	Bit-Width Reduction for Ising Models Proving the Ground State by Topologically Isomorphic n-Partition. ICCE Shu Tomita, Raio Aoki, Shinnosuke Inaba, Masashi Tawada, Nozomu Togawa
2026	J	`jnl`	Leveraging Non-Exact QUBO Formulation With Quantum Annealing to Optimize 5G Base Station Power Selection. IEEE Access Chihiro Dogo, Kazuhiro Saito, Masashi Tawada, Nozomu Togawa
2025	C	`conf`	An Ising Machine-Based Hybrid Optimization Method Using Constraint Conversion and Correction. ICCE Kinya Iwata, Masashi Tawada, Nozomu Togawa
2024	—	`conf`	A Novel Classical-Ising Hybrid Annealing Method with QUBO Model Cutting. MWSCAS Yuta Atobe, Masashi Tawada, Nozomu Togawa
2024	J	`jnl`	An Ising-Machine-Based Solver of Vehicle Routing Problem With Balanced Pick-Up. IEEE Trans. Consumer Electron. Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
2024	Misc	`conf`	Non-zero Coefficients Removing Method to Improve the Ising Machine Solving Performance. QCE Kinya Iwata, Masashi Tawada, Nozomu Togawa
2024	C	`conf`	Optimization of Practical Time-Dependent Vehicle Routing Problem by Ising Machines. ICCE Yui Tsuyumine, Kenichi Masuda, Takeshi Hachikawa, Tsuyoshi Haga, Yuta Yachi, Tatsuhiko Shirai, Masashi Tawada, Nozomu Togawa
2024	Misc	`conf`	QUBO Coefficient Dynamic Ratio Shrinking Method for Quantum Annealers. QCE Yuta Yachi, Masashi Tawada, Nozomu Togawa
2023	—	`conf`	A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State Output. SOCC Yuta Yachi, Masashi Tawada, Nozomu Togawa
2023	J	`jnl`	An Efficient Combined Bit-Width Reducing Method for Ising Models. IEICE Trans. Inf. Syst. Yuta Yachi, Masashi Tawada, Nozomu Togawa
2022	C	`conf`	Efficient Coefficient Bit-Width Reduction Method for Ising Machines. ICCE Yuta Yachi, Yousuke Mukasa, Masashi Tawada, Nozomu Togawa
2022	J	`jnl`	How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins. IEEE Trans. Computers Daisuke Oku, Masashi Tawada, Shu Tanaka, Nozomu Togawa
2022	J	`jnl`	Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances. IEEE Trans. Computers Yuta Atobe, Masashi Tawada, Nozomu Togawa
2022	C	`conf`	QUBO Matrix Distorting Method for Consumer Applications. ICCE Tomokazu Yoshimura, Tatsuhiko Shirai, Masashi Tawada, Nozomu Togawa
2021	—	`conf`	An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines. VLSI-DAT Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
2021	J	`jnl`	Mapping Induced Subgraph Isomorphism Problems to Ising Models and Its Evaluations by an Ising Machine. IEICE Trans. Inf. Syst. Natsuhito Yoshimura, Masashi Tawada, Shu Tanaka, Junya Arai, Satoshi Yagi, Hiroyuki Uchiyama, Nozomu Togawa
2021	—	`conf`	Multi-day Travel Planning Using Ising Machines for Real-world Applications. ITSC Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
2021	C	`conf`	Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture. ICCE Shota Matsuno, Masashi Tawada, Nozomu Togawa
2020	C	`conf`	A New LDPC Code Decoding Method: Expanding the Scope of Ising Machines. ICCE Masashi Tawada, Shu Tanaka, Nozomu Togawa
2020	—	`conf`	Designing Stochastic Number Generators Sharing a Random Number Source based on the Randomization Function. NEWCAS Masashi Tawada, Nozomu Togawa
2020	—	`conf`	FPGA-based Heterogeneous Solver for Three-Dimensional Routing. ASP-DAC Kento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa
2020	—	`conf`	Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation. LASCAS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2020	J	`jnl`	Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design. IPSJ Trans. Syst. LSI Des. Methodol. Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2019	—	`conf`	Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder. MWSCAS Yuta Ideguchi, Norifumi Kamiya, Masashi Tawada, Nozomu Togawa
2019	—	`conf`	Efficient Ising Model Mapping for Induced Subgraph Isomorphism Problems Using Ising Machines. ICCE-Berlin Natsuhito Yoshimura, Masashi Tawada, Shu Tanaka, Junya Arai, Satoshi Yagi, Hiroyuki Uchiyama, Nozomu Togawa
2019	C	`conf`	Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
2019	C	`conf`	Error Correction Coding of Stochastic Numbers Using BER Measurement. IOLTS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2019	—	`conf`	Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels. ICECS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement. NGCAS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2018	C	`conf`	An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. IOLTS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2017	C	`conf`	Effective write-reduction method for MLC non-volatile memory. ISCAS Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	A bit-write reduction method based on error-correcting codes for non-volatile memories. ASP-DAC Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2015	A	`conf`	Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. ICCAD Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	A write-reducing and error-correcting code generation method for non-volatile memories. APCCAS Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2013	—	`conf`	Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi
2011	J	`jnl`	Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. Inf. Media Technol. Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	Speeding-up exact and fast FIFO-based cache configuration simulation. IEICE Electron. Express Masashi Tawada, Masao Yanagisawa, Nozomu Togawa