Masashi Imai - RankMe

56 papers A 1B 1C 9Misc 1Journal 10Unranked 34

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Simulation and Evaluation of Asynchronous Circuits in Extreme Edge Environments. ISMVL Masashi Imai
2021	—	`conf`	An Energy Efficient Processor Applicable to Continuous SPO2 Monitoring. GCCE Kan Hatakeyama, Seria Kasai, Masashi Imai, Atsushi Kurokawa, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara
2020	J	`jnl`	A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis. IEICE Electron. Express Toshiki Kanamoto, Koki Kasai, Kan Hatakeyama, Atsushi Kurokawa, Tomoyuki Nagase, Masashi Imai
2020	—	`conf`	Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices. ASYNC Tomohiro Yoneda, Masashi Imai
2019	—	`conf`	A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck. MWSCAS Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai
2019	J	`jnl`	Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133). NII Shonan Meet. Rep. Tomohiro Yoneda, Peter A. Beerel, Alex Yakovlev, Masashi Imai
2019	—	`conf`	Hardware Trojan Insertion and Detection in Asynchronous Circuits. ASYNC Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
2018	J	`jnl`	MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
2018	—	`conf`	Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. ASYNC Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda
2017	—	`conf`	Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs. ISQED Kaoru Furumi, Masashi Imai, Atsushi Kurokawa
2017	—	`conf`	MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda
2017	J	`jnl`	Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
2016	—	`conf`	A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks. MCSoC Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
2016	C	`conf`	A task allocation method for the DTTR scheme based on task scheduling of fault patterns. ISCAS Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
2016	—	`conf`	The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. NOCS Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda
2015	C	`conf`	A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits. ICCD Tomohiro Yoneda, Masashi Imai
2015	—	`conf`	An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs. ISQED Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa
2015	—	`conf`	Clock skew reduction for stacked chips using multiple source buffers. ISCIT Nanako Niioka, Masashi Imai, Masa-Aki Fukase, Yuuki Miura, Kaoru Furumi, Atsushi Kurokawa
2015	—	`conf`	Dependable real-time task execution scheme for a many-core platform. DFTS Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise
2015	J	`jnl`	Novel Implementation Method of Multiple-Way Asynchronous Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masashi Imai, Tomohiro Yoneda
2015	J	`jnl`	Signal Propagation Delay Model in Vertically Stacked Chips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nanako Niioka, Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa
2014	—	`conf`	An NoC-based evaluation platform for safety-critical automotive applications. APCCAS Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura
2014	—	`conf`	Effect of substrate contacts on reducing crosstalk noise between TSVs. APCCAS Masayuki Watanabe, Rosely Karel, Nanako Niioka, Tetsuya Kobayashi, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa
2014	—	`conf`	Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits. APCCAS Masashi Imai, Tomohiro Yoneda
2014	J	`jnl`	High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
2014	—	`conf`	Impact of on-chip interconnects on vertical signal propagation in 3D ICs. APCCAS Nanako Niioka, Masayuki Watanabe, Rosely Karel, Tetsuya Kobayashi, Masashi Imai, Masa-Aki Fukase, Atsushi Kurokawa
2014	—	`conf`	Modeling of substrate contacts in TSV-based 3D ICs. 3DIC Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Atsushi Kurokawa
2014	C	`conf`	Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. ISCAS Masashi Imai, Tomohiro Yoneda
2013	J	`jnl`	Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories. IEICE Trans. Inf. Syst. Masashi Imai, Tomohiro Yoneda
2012	—	`conf`	Dependable routing in multi-chip NoC platforms for automotive applications. DFT Tomohiro Yoneda, Masashi Imai
2012	C	`conf`	Multi-chip NoCs for Automotive Applications. PRDC Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2012	C	`conf`	Performance Modeling and Analysis of On-chip Networks for Real-Time Applications. PRDC Masashi Imai, Tomohiro Yoneda
2011	—	`conf`	Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories. DFT Masashi Imai, Tomohiro Yoneda
2011	—	`conf`	Improving Dependability and Performance of Fully Asynchronous On-chip Networks. ASYNC Masashi Imai, Tomohiro Yoneda
2010	C	`conf`	An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors. PRDC James L. Weston, Masashi Imai, Tomohide Nagai, Takashi Nanya
2010	—	`conf`	Pair and swap: An approach to graceful degradation for dependable chip multiprocessors. DSN Workshops Masashi Imai, Tomohide Nagai, Takashi Nanya
2009	Misc	`conf`	Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura
2009	—	`conf`	Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors. ASYNC Masashi Imai, Kouei Takada, Takashi Nanya
2009	C	`conf`	N-way ring and square arbiters. ICCD Masashi Imai, Tomohiro Yoneda, Takashi Nanya
2008	—	`conf`	A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. ACSD Masashi Imai, Takashi Nanya
2007	A	`conf`	Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. DATE Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
2006	—	`conf`	A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ASYNC Masashi Imai, Takashi Nanya
2006	J	`jnl`	Design Method of High Performance and Low Power Functional Units Considering Delay Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
2004	C	`conf`	Asynchronous Scan-Latch controller for Low Area Overhead DFT. ICCD Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
2004	—	`conf`	Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. ASYNC Masashi Imai, Metehan Özcan, Takashi Nanya
2004	B	`conf`	Skewed Checkpointing for Tolerating Multi-Node Failures. SRDS Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya
2003	—	`conf`	A zero-time-overhead asynchronous four-phase controller. ISCAS (5) Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya
2003	—	`conf`	Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. ASYNC Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
2003	—	`conf`	Control signal sharing of asynchronous circuits using datapath delay information. ISCAS (5) Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya
2003	J	`jnl`	Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nattha Sretasereekul, Hiroshi Saito, Euiseok Kim, Metehan Özcan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
2002	—	`conf`	Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. APCCAS (1) T. Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura
2002	—	`conf`	Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. ASYNC Metehan Özcan, Masashi Imai, Takashi Nanya
2002	—	`conf`	High Throughput Asynchronous Domino Using Dual output Buffer. IWLS Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
2001	—	`conf`	Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ASYNC Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno
1998	—	`conf`	TITAC-2: An Asynchronous 32-bit Microprocessor. ASP-DAC Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya
1997	C	`conf`	TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. ICCD Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya