Masashi Horiguchi

21 papers C 1Journal 14Unranked 4
YearRankTypeTitle / Venue / Authors
2020 — conf
Simple Reference Voltage Generation Circuit Insensitive to Temperature.
ISOCC
Lei Sha, Anna Kuwana, Masashi Horiguchi, Haruo Kobayashi
2012 — conf
A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from -50°C to +150°C using piecewise-linear-current curvature compensation.
VLSIC
Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi, Moriyoshi Ota
2011 — conf
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs.
CICC
Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi
2011 — book
Nanoscale Memory Repair
Masashi Horiguchi, Kiyoo Itoh
2007 — conf
Low-voltage limitations of memory-rich nano-scale CMOS LSIs.
ESSCIRC
Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka
2007 — book
Ultra-Low Voltage Nano-Scale Memories
Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka
2006 C conf
Ultra-low voltage nano-scale embedded RAMs.
ISCAS
Kiyoo Itoh, Masashi Horiguchi, Takayuki Kawahara
2003 J jnl
Review and future prospects of low-voltage RAM circuits.
IBM J. Res. Dev.
Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara, Kiyoo Itoh
1995 J jnl
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.
IEEE J. Solid State Circuits
Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda
1995 J jnl
Low-noise, high-speed data transmission using a ringing-canceling output buffer.
IEEE J. Solid State Circuits
Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki
1994 J jnl
A charge recycle refresh for Gb-scale DRAM's in file applications.
IEEE J. Solid State Circuits
Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki
1994 J jnl
Subthreshold-current reduction circuits for multi-gigabit DRAM's.
IEEE J. Solid State Circuits
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
1994 J jnl
Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's.
IEEE J. Solid State Circuits
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
1993 J jnl
256-Mb DRAM circuit technologies for file applications.
IEEE J. Solid State Circuits
Goro Kitsukawa, Masashi Horiguchi, Yoshiki Kawajiri, Takayuki Kawahara, Takesada Akiba, Yasushi Kawase, Toshikazu Tachibana, Takeshi Sakai, Masakazu Aoki, Syoji Shukuri, Kazuhiko Sagara, Ryo Nagai, Yuzuru Ohji, Nono Hasegawa, Natsuki Yokoyama, Teruaki Kisu, Hisaomi Yamashita, Tokuo Kure, Takashi Nishida
1993 J jnl
Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs).
IEEE J. Solid State Circuits
Takayuki Kawahara, Masashi Horiguchi, Yoshiki Kawajiri, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki
1993 J jnl
Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's.
IEEE J. Solid State Circuits
Masashi Horiguchi, Takeshi Sakata, Kiyoo Itoh
1991 J jnl
A flexible redundancy technique for high-density DRAMs.
IEEE J. Solid State Circuits
Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh, Tetsuro Matsumoto
1991 J jnl
Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test.
IEEE J. Solid State Circuits
Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Gyoo Itoh, Kazuhiko Kajigaya, Atsushi Nozoe, Tetsuro Matsumoto
1990 J jnl
A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier.
IEEE J. Solid State Circuits
Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto
1989 J jnl
New DRAM noise generation under half-V
IEEE J. Solid State Circuits
Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh
1988 J jnl
An experimental large-capacity semiconductor file memory using 16-levels/cell storage.
IEEE J. Solid State Circuits
Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi