Masaru Osada

12 papers Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2025 — conf
A 96fsrms-Jitter, -70.6dBc-Fractional-Spur Cascaded PLL Employing Two MMDs with Shared DSM for Quantization Noise Cancellation.
ISSCC
Haoming Zhang, Yuyang Zhu, Masaru Osada, Tetsuya Iizuka
2025 J jnl
A Fractional-N Cascaded PLL With MMD-Based Quantization-Error Cancellation.
IEEE J. Solid State Circuits
Haoming Zhang, Yuyang Zhu, Masaru Osada, Tetsuya Iizuka
2025 J jnl
A Harmonic-Mixer-Based Fractional-N PLL Employing Voltage-Domain Feed-Forward Noise Cancellation.
IEEE J. Solid State Circuits
Haoming Zhang, Masaru Osada, Yuyang Zhu, Tetsuya Iizuka
2025 J jnl
Optimization of DTC-Based and Harmonic-Mixer-Based Fractional-N PLLs: Comparative Analysis of Jitter and Power Trade-Offs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuyang Zhu, Masaru Osada, Haoming Zhang, Tetsuya Iizuka
2024 J jnl
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering.
IEEE J. Solid State Circuits
Masaru Osada, Zule Xu, Zunsong Yang, Tetsuya Iizuka
2024 J jnl
Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuyang Zhu, Zunsong Yang, Masaru Osada, Haoming Zhang, Tetsuya Iizuka
2023 — conf
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load.
VLSI Technology and Circuits
Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka
2022 — conf
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter.
VLSI Technology and Circuits
Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka
2022 — conf
An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering.
ESSCIRC
Masaru Osada, Zule Xu, Tetsuya Iizuka
2022 J jnl
Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Masaru Osada, Zule Xu, Ryoya Shibata, Tetsuya Iizuka
2021 — conf
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur.
VLSI Circuits
Zule Xu, Masaru Osada, Tetsuya Iizuka
2020 — conf
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur.
VLSI Circuits
Masaru Osada, Zule Xu, Tetsuya Iizuka