Masao Yanagisawa

220 papers A* 1A 3C 25Journal 100Unranked 91

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	An FPGA-Based YOLOv6 Accelerator for High-Throughput and Energy-Efficient Object Detection. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xingan Sha, Masao Yanagisawa, Youhua Shi
2025	J	`jnl`	DSE-Based Hardware Trojan Attack for Neural Network Accelerators on FPGAs. IEEE Trans. Neural Networks Learn. Syst. Chao Guo, Masao Yanagisawa, Youhua Shi
2023	—	`conf`	An Area-Power-Efficient Multiplier-less Processing Element Design for CNN Accelerators. ASICON Jiaxiang Li, Masao Yanagisawa, Youhua Shi
2023	—	`conf`	Strategy for Improving Cycle of Maximized Energy Output of Triboelectric Nanogenerators. ICICDT Yirui Su, Masao Yanagisawa, Youhua Shi
2021	J	`jnl`	Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow. IEEE Access Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi
2020	—	`conf`	A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters. APCCAS Jinghao Ye, Masao Yanagisawa, Youhua Shi
2020	J	`jnl`	Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jinghao Ye, Masao Yanagisawa, Youhua Shi
2020	—	`conf`	Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation. LASCAS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2020	J	`jnl`	Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design. IPSJ Trans. Syst. LSI Des. Methodol. Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2020	J	`jnl`	Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets. IEEE Trans. Circuits Syst. II Express Briefs Saki Tajima, Masao Yanagisawa, Youhua Shi
2020	J	`jnl`	Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures. IEICE Trans. Inf. Syst. Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2019	—	`conf`	A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing. APCCAS Jinghao Ye, Masao Yanagisawa, Youhua Shi
2019	J	`jnl`	A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2019	J	`jnl`	A Robust Indoor/Outdoor Detection Method Based on Spatial and Temporal Features of Sparse GPS Measured Positions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2019	—	`conf`	A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments. ICIS (best papers) Siya Bao, Masao Yanagisawa, Nozomu Togawa
2019	—	`conf`	A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks. APCCAS Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi
2019	—	`conf`	An Adder-Segmentation-based FIR for High Speed Signal Processing. ASICON Jinghao Ye, Masao Yanagisawa, Youhua Shi
2019	J	`jnl`	An FPGA Implementation Method based on Distributed-register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2019	J	`jnl`	Bicycle Behavior Recognition Using 3-Axis Acceleration Sensor and 3-Axis Gyro Sensor Equipped with Smartphone. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuri Usami, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2019	C	`conf`	Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
2019	C	`conf`	Error Correction Coding of Stochastic Numbers Using BER Measurement. IOLTS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2019	—	`conf`	Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels. ICECS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2019	C	`conf`	Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. ISCAS Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2018	—	`conf`	2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement. NGCAS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2018	—	`conf`	A Multiple Cyclic-Route Generation Method for Strolling Based on Point-of-Interests. ICCE-Berlin Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2018	C	`conf`	A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. ISCAS Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2018	C	`conf`	A hardware-Trojan classification method utilizing boundary net structures. ICCE Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	A loop structure optimization targeting high-level synthesis of fast number theoretic transform. ISQED Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2018	C	`conf`	An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. IOLTS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	An Ising model mapping to solve rectangle packing problem. VLSI-DAT Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	Bicycle Behavior Recognition using Sensors Equipped with Smartphone. ICCE-Berlin Yuri Usami, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach. ICCE-Berlin Tomotaka Inoue, Kento Hasegawa, Yuki Kobayashi, Masao Yanagisawa, Nozomu Togawa
2018	C	`conf`	Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis. IOLTS Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2018	—	`conf`	Gesture recognition of air-tapping and its application to character input in VR space. SIGGRAPH ASIA Posters Mamoru Hirota, Ayumu Tsuboi, Masayuki Yokoyama, Masao Yanagisawa
2018	J	`jnl`	Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masaru Oya, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis. IEEE BigData Siya Bao, Masao Yanagisawa, Nozomu Togawa
2018	C	`conf`	Road-illuminance level inference across road networks based on Bayesian analysis. ICCE Siya Bao, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	Robust Indoor/Outdoor Detection Method based on Sparse GPS Positioning Information. ICCE-Berlin Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures. IPSJ Trans. Syst. LSI Des. Methodol. Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koki Igawa, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Siya Bao, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	A low cost and high speed CSD-based symmetric transpose block FIR implementation. ASICON Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa
2017	A*	`conf`	A proposal for wearable controller device and finger gesture recognition using surface electromyography. SIGGRAPH ASIA (Posters) Ayumu Tsuboi, Mamoru Hirota, Junki Sato, Masayuki Yokoyama, Masao Yanagisawa
2017	—	`conf`	A robust scan-based side-channel attack method against HMAC-SHA-256 circuits. ICCE-Berlin Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	A selector-based FFT processor and its FPGA implementation. ISOCC Yuya Hirai, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	A stayed location estimation method for sparse GPS positioning information. GCCE Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	An Evaluation of Hand-Force Prediction Using Artificial Neural-Network Regression Models of Surface EMG Signals for Handwear Devices. J. Sensors Masayuki Yokoyama, Ryohei Koyama, Masao Yanagisawa
2017	—	`conf`	An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons. GCCE Ryoya Momose, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	Designing hardware trojans and their detection based on a SVM-based approach. ASICON Tomotaka Inoue, Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2017	C	`conf`	Effective write-reduction method for MLC non-volatile memory. ISCAS Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. ASICON Daiki Asai, Masao Yanagisawa, Nozomu Togawa
2017	C	`conf`	Hardware Trojan detection and classification based on steady state learning. IOLTS Masaru Oya, Masao Yanagisawa, Nozomu Togawa
2017	C	`conf`	Hardware Trojans classification for gate-level netlists using multi-layer neural networks. IOLTS Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	Personalized one-day travel with multi-nearby-landmark recommendation. ICCE-Berlin Siya Bao, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	Robust AES circuit design for delay variation using suspicious timing error prediction. ISOCC Yuki Yahagi, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	Soft error tolerant latch designs with low power consumption (invited paper). ASICON Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2017	J	`jnl`	Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2017	C	`conf`	Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier. ISCAS Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koki Igawa, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	A delay variation and floorplan aware high-level synthesis algorithm with body biasing. ISQED Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	A high-performance circuit design algorithm using data dependent approximation. ISOCC Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	A safe and comprehensive route finding method for pedestrian based on lighting and landmark. GCCE Siya Bao, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	Bi-Partitioning Based Multiplexer Network for Field-Data Extractors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning. GCCE Keisuke Kono, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
2016	C	`conf`	Hardware Trojans classification for gate-level netlists based on machine learning. IOLTS Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masaru Oya, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	Implementation evaluation of scan-based attack against a Trivium cipher circuit. APCCAS Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	In-situ Trojan authentication for invalidating hardware-Trojan functions. ISQED Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms. IEICE Electron. Express Koki Igawa, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	Pedestrian navigation based on landmark recognition using glass-type wearable devices. GCCE Ryoya Yano, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
2016	C	`conf`	Redesign for untrusted gate-level netlists. IOLTS Masaru Oya, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	Rotator-based multiplexer network synthesis for field-data extractors. SoCC Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2016	C	`conf`	Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices. ISCAS Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	A bit-write reduction method based on error-correcting codes for non-volatile memories. ASP-DAC Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2015	C	`conf`	A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. ISCAS Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	A landmark-based route recommendation method for pedestrian walking strategies. GCCE Siya Bao, Tomoyuki Nitta, Daisuke Shindou, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	A low-power soft error tolerant latch scheme. ASICON Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa
2015	—	`conf`	A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. SoCC Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015	A	`conf`	A score-based classification method for identifying hardware-trojans at gate-level netlists. DATE Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	A visible corner-landmark based route finding algorithm for pedestrian navigation. GCCE Kengo Takeda, Tomoyuki Nitta, Daisuke Shindou, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2015	A	`conf`	Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. ICCAD Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Clock skew estimate modeling for FPGA high-level synthesis and its application. ASICON Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. Inf. Media Technol. Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. ASICON Keita Igarashi, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation. ASICON Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Muscle analysis of hand and forearm during tapping using surface electromyography. GCCE Masayuki Yokoyama, Ryohei Koyama, Masao Yanagisawa
2015	—	`conf`	Partitioning-based multiplexer network synthesis for field-data extractors. SoCC Koki Ito, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Huiqian Jiang, Mika Fujishiro, Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Small-sized and noise-reducing power analyzer design for low-power IoT devices. ASICON Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
2014	J	`jnl`	A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. Inf. Media Technol. Yuta Hagio, Masao Yanagisawa, Nozomu Togawa
2014	J	`jnl`	A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. Yuta Hagio, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. APCCAS Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. APCCAS Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	A write-reducing and error-correcting code generation method for non-volatile memories. APCCAS Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. APCCAS Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2014	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. IPSJ Trans. Syst. LSI Des. Methodol. Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2014	C	`conf`	Linear and bi-linear interpolation circuits using selector logics and their evaluations. ISCAS Masashi Shio, Masao Yanagisawa, Nozomu Togawa
2014	J	`jnl`	Scan-Based Attack against Trivium Stream Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
2014	J	`jnl`	Scan-Based Side-Channel Attack on the LED Block Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
2014	C	`conf`	Scan-based attack on the LED block cipher using scan signatures. ISCAS Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	Scan-based side-channel attack on Camellia cipher using scan signatures. APCCAS Huiqian Hang, Mika Fujishiro, Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	Secure scan design using improved random order and its evaluations. APCCAS Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	Throughput driven check point selection in suspicious timing error prediction based designs. LASCAS Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2013	C	`conf`	A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. ISCAS Kazushi Kawamura, Sho Tanaka, Masao Yanagisawa, Nozomu Togawa
2013	—	`conf`	An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. VLSI-DAT Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2013	C	`conf`	Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. ISCAS Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2013	—	`conf`	Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi
2013	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. Inf. Media Technol. Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. IPSJ Trans. Syst. LSI Des. Methodol. Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures. Inf. Media Technol. Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures. J. Inf. Process. Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2013	—	`conf`	Scan-based attack against Trivium stream cipher independent of scan structure. ASICON Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
2013	C	`conf`	Secure Scan Design with Dynamically Configurable Connection. PRDC Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2013	—	`conf`	Suspicious timing error prediction with in-cycle clock gating. ISQED Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa
2012	J	`jnl`	A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution. IPSJ Trans. Syst. LSI Des. Methodol. Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Seungju Lee, Masao Yanagisawa, Nozomu Togawa
2012	C	`conf`	An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. ISCAS Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2012	—	`conf`	Dynamically changeable secure scan architecture against scan-based side channel attack. ISOCC Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architectures. Inf. Media Technol. Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2012	—	`conf`	Energy-efficient high-level synthesis for HDR architectures with clock gating. ISOCC Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	Integrating Wearable Sensor Technology into Project-management Process. Inf. Media Technol. Koji Ara, Tomoaki Akitomi, Nobuo Sato, Kunio Takahashi, Hideyuki Maeda, Kazuo Yano, Masao Yanagisawa
2012	J	`jnl`	Integrating Wearable Sensor Technology into Project-management Process. J. Inf. Process. Koji Ara, Tomoaki Akitomi, Nobuo Sato, Kunio Takahashi, Hideyuki Maeda, Kazuo Yano, Masao Yanagisawa
2012	J	`jnl`	MH IEICE Electron. Express Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. IEEE Trans. Very Large Scale Integr. Syst. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2012	J	`jnl`	Scan-Based Attack on AES through Round Registers and Its Countermeasure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Masao Yanagisawa
2012	—	`conf`	Scan-based attack against DES cryptosystems using scan signatures. APCCAS Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2012	—	`conf`	State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit. APCCAS Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2012	—	`conf`	Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. APCCAS Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa
2011	J	`jnl`	A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. Inf. Media Technol. Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. IPSJ Trans. Syst. LSI Des. Methodol. Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. Sho Tanaka, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. Inf. Media Technol. Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto
2011	J	`jnl`	Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto
2011	J	`jnl`	Scan Vulnerability in Elliptic Curve Cryptosystems. IPSJ Trans. Syst. LSI Des. Methodol. Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2011	J	`jnl`	Speeding-up exact and fast FIFO-based cache configuration simulation. IEICE Electron. Express Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2010	—	`conf`	A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. APCCAS Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2010	—	`conf`	BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers. APCCAS Seungju Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2010	J	`jnl`	Improved Launch for Higher TDF Coverage With Fewer Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010	C	`conf`	Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. ISCAS Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010	J	`jnl`	Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2010	—	`conf`	Scan-based attack against elliptic curve cryptosystems. ASP-DAC Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010	C	`conf`	State-dependent changeable scan architecture against scan-based side channel attacks. ISCAS Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010	—	`conf`	VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding. APCCAS Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	A Scan-Based Attack Based on Discriminators for AES Cryptosystems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	A Two-Level Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	An L1 Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	A	`conf`	Design-for-secure-test for crypto cores. ITC Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	—	`conf`	Exact and fast L1 cache simulation for embedded systems. ASP-DAC Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	J	`jnl`	A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Trans. Inf. Syst. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	J	`jnl`	A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	—	`conf`	Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. APCCAS Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	—	`conf`	FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm. APCCAS Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Makoto Satoh
2008	J	`jnl`	Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. Inf. Media Technol. Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	J	`jnl`	Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	—	`conf`	GECOM: Test data compression combined with all unknown response masking. ASP-DAC Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	J	`jnl`	Robust estimation of the arterial input function for Logan plots using an intersectional searching algorithm and clustering in positron emission tomography for neuroreceptor imaging. NeuroImage Mika Naganawa, Yuichi Kimura, Junichi Yano, Masahiro Mishina, Masao Yanagisawa, Kenji Ishii, Keiichi Oda, Kiichi Ishiwata
2008	—	`conf`	Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2 ASP-DAC Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	—	`conf`	Unknown response masking with minimized observable response loss and mask data. APCCAS Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2007	J	`jnl`	Accurate automated clustering of two-dimensional data for single-nucleotide polymorphism genotyping by a combination of clustering methods: evaluation by large-scale real data. Bioinform. Shuichi Takitoh, Shogo Fujii, Yoichi Mase, Junichi Takasaki, Toshimasa Yamazaki, Yozo Ohnishi, Masao Yanagisawa, Yusuke Nakamura, Naoyuki Kamatani
2007	C	`conf`	Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2006	J	`jnl`	A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. IEICE Trans. Electron. Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2006	—	`conf`	An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ASP-DAC Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2006	—	`conf`	FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2006	—	`conf`	Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. DFT Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito
2006	J	`jnl`	Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2005	J	`jnl`	A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. IEICE Trans. Inf. Syst. Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2005	—	`conf`	A processor core synthesis system in IP-based SoC design. ASP-DAC Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2005	—	`conf`	Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura
2005	J	`jnl`	Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2005	—	`conf`	Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. ISCAS (4) Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2004	—	`conf`	A cosynthesis algorithm for application specific processors with heterogeneous datapaths. ASP-DAC Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2004	—	`conf`	A thread partitioning algorithm in low power high-level synthesis. ASP-DAC Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2004	—	`conf`	Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2004	—	`conf`	Instruction set and functional unit synthesis for SIMD processor cores. ASP-DAC Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2003	J	`jnl`	A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2003	J	`jnl`	A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nozomu Togawa, Takao Totsuka, Tatsuhiko Wakui, Masao Yanagisawa, Tatsuo Ohtsuki
2003	J	`jnl`	A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2003	J	`jnl`	A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki
2003	—	`conf`	A hardware/software partitioning algorithm for SIMD processor cores. ASP-DAC Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki
2002	J	`jnl`	A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002	J	`jnl`	An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002	—	`conf`	An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. APCCAS (1) Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002	J	`jnl`	High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002	—	`conf`	VLSI Architecture for a Flexible Motion Estimation with Parameters. ASP-DAC/VLSI Design Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2001	—	`conf`	Area/delay estimation for digital signal processor cores. ASP-DAC Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2000	—	`conf`	An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). ASP-DAC Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki
1999	—	`conf`	A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. ASP-DAC Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki
1999	J	`jnl`	A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. J. Circuits Syst. Comput. Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki
1999	J	`jnl`	Fast Motion Estimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlations. J. Circuits Syst. Comput. Tingrong Zhao, Masao Yanagisawa, Tatsuo Ohtsuki
1998	—	`conf`	A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. ASP-DAC Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki
1998	—	`conf`	An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. ASP-DAC Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki
1998	J	`jnl`	Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki