Masao Nakaya

13 papers A* 2C 2Journal 9
YearRankTypeTitle / Venue / Authors
2008 J jnl
Special Section on Advanced Technologies in Digital LSIs and Memories.
IEICE Trans. Electron.
Masao Nakaya
2007 J jnl
Roundtable: Envisioning the Future for Multiprocessor SoC.
IEEE Des. Test Comput.
Ahmed Amine Jerraya, Olivier Franza, Markus Levy, Masao Nakaya, Pierre G. Paulin, Ulrich Ramacher, Deepu Talla, Wayne H. Wolf
2000 J jnl
14-bit 2.2-MS/s sigma-delta ADC's.
IEEE J. Solid State Circuits
James C. Morizio, Michael Hoke, Taskin Koçak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Michael H. Hood, George Lynch, Harufusa Kondoh, Toshio Kumamoto, Takashi Okuda, Hiroshi Noda, Masahiko Ishiwaki, Takahiro Miki, Masao Nakaya
2000 C conf
SNDR sensitivity analysis for cascaded ΣΔ modulators.
ISCAS
James C. Morizio, Mike Hoke, Taskin Koçak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Mike Hood, Ward Huffman, Takashi Okuda, Hiroshi Noda, Yasuo Morimoto, Toshio Kumamoto, Masahiko Ishiwaki, Harufusa Kondoh, Masao Nakaya, Takahiro Miki
1998 J jnl
Software pipelining with path selection.
Syst. Comput. Jpn.
Chikako Nakanishi, Hideki Ando, Tetsuya Hara, Masao Nakaya
1996 A* conf
Performance Comparison of ILP Machines with Cycle Time Evaluation.
ISCA
Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya
1995 J jnl
Code scheduling on a superscalar processor: SARCH.
Syst. Comput. Jpn.
Chikako Nakanishi, Hideki Ando, Hirohisa Machida, Masao Nakaya
1995 A* conf
Unconstrained Speculative Execution with Predicated State Buffering.
ISCA
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya
1993 J jnl
A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture.
IEEE J. Solid State Circuits
Harufusa Kondoh, Hiromi Notani, Hideaki Yamanaka, Keiichi Higashitani, Hirotaka Saito, Isamu Hayashi, Shigeki Kohama, Yoshio Matsuda, Kazuyoshi Oshima, Masao Nakaya
1993 J jnl
A VLSI chip set for a large-scale parallel inference machine: PIM/m.
IEEE J. Solid State Circuits
Hirohisa Machida, Hideki Ando, Kenichi Yasuda, Kiyohiro Furutani, Yukihiro Yamashita, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Masayoshi Sakao, Masao Nakaya
1993 C conf
Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine.
ICCD
Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya
1988 J jnl
A DSP line equalizer VLSI for TCM digital subscriber-line transmission.
IEEE J. Solid State Circuits
Hideki Ando, Masao Nakaya, Hiroki Hona, Ihuo Iizuka, Yasutaka Horiba
1988 J jnl
An SOI structure for flash A/D converter.
IEEE J. Solid State Circuits
Toshio Kumamoto, Masao Nakaya, Shigeru Kusunoki, Tadashi Nishimura, Nobuharu Yazawa, Yoichi Akasaka, Yasutaka Horiba