Masao Morimoto

14 papers Journal 4Unranked 10
YearRankTypeTitle / Venue / Authors
2026 — conf
A 3nm 0.167fJ/b 5.27Mb/mm
ISSCC
Shunya Nagata, Yohei Sawada, Kenichiro Takiguchi, Masao Morimoto, Shinji Tanaka, Naoya Fujita, Tomohiro Miura, Daisuke Nakamura, Takashi Ito
2020 — conf
A 29.2 Mb/mm
VLSI Circuits
Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, Masao Morimoto, Makoto Yabuuchi, Yuichiro Ishii, Shinji Tanaka
2020 — conf
A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier.
VLSI Circuits
Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka
2018 — conf
12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM.
VLSI Circuits
Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka
2016 — conf
A 5.92-Mb/mm
A-SSCC
Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii
2015 — conf
1.8 Mbit/mm
VLSIC
Yasumasa Tsukamoto, Masao Morimoto, Makoto Yabuuchi, Miki Tanaka, Koji Nii
2014 — conf
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists.
ISSCC
Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii
2013 J jnl
A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS.
IEEE J. Solid State Circuits
Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki
2012 — conf
A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS.
VLSIC
Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Yasuhisa Shimazaki
2009 — conf
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation.
CICC
Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada
2007 J jnl
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations.
IEICE Trans. Electron.
Masao Morimoto, Makoto Nagata, Kazuo Taki
2005 J jnl
High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition.
IEICE Trans. Electron.
Masao Morimoto, Makoto Nagata, Kazuo Taki
2005 J jnl
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masao Morimoto, Yoshinori Tanaka, Makoto Nagata, Kazuo Taki
2002 — conf
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm.
CICC
Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto