Masanori Natsui

60 papers A 3B 2C 5Journal 17Unranked 33

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	An FPGA-based rapid-prototyping platform for spintronics-based edge-computing hardware. ISMVL Daisuke Suzuki, Akira Tamakoshi, Tomohiro Yoneda, Masanori Natsui, Yasuhiro Takako, Takahiro Hanyu
2025	C	`conf`	Design of a Low-Energy MTJ-Based Nonvolatile Register Based on a Differential Information Storing Scheme. ISCAS Tomoo Yoshida, Masanori Natsui, Takahiro Hanyu
2025	J	`jnl`	Design of a single-capacitor-based threshold-adjustable power management circuit for task-aware waste-minimized energy harvesting. IEICE Electron. Express Fangcen Zhong, Masanori Natsui, Takahiro Hanyu
2025	J	`jnl`	Design of an Intermittent-Computing-Oriented Nonvolatile Register With a Switching-Probability-Aware Store-and-Verify Scheme. IEEE Access Masanori Natsui, Takahiro Hanyu
2025	—	`conf`	Implementation of an MRAM-Based Edge AI Hardware with a Fine-Grained Power-Gating Technique. ISMVL Tomohiro Yoneda, Yasuhiro Takako, Akira Tamakoshi, Masanori Natsui, Daisuke Suzuki, Takahiro Hanyu
2025	—	`conf`	Intelligent Power-Gating Technique with Quick Wake-Up/Sleep Functionality for Spintronics-Based Edge Computing Hardware. ISMVL Fangcen Zhong, Masanori Natsui, Takahiro Hanyu
2024	B	`conf`	Design of a High-Speed and Low-Power Threshold Adjustment Unit for Battery-Free Edge Devices. IJCNN Fangcen Zhong, Masanori Natsui, Takahiro Hanyu
2024	—	`conf`	Design of an Energy/Area-Aware MTJ-Based Nonvolatile Register with a Reference-Load Sharing Scheme. MWSCAS Tomoo Yoshida, Masanori Natsui, Takahiro Hanyu
2024	J	`jnl`	Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware. IEICE Trans. Inf. Syst. Ken Asano, Masanori Natsui, Takahiro Hanyu
2024	—	`conf`	Error-Tolerant Quantized Neural Network Based on Non-Weighted Arithmetic. ISMVL Masanori Natsui, Ken Asano, Takahiro Hanyu
2023	—	`conf`	Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing. MWSCAS Kaede Sakai, Masanori Natsui, Takahiro Hanyu
2023	—	`conf`	Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network. ICECS Ken Asano, Masanori Natsui, Takahiro Hanyu
2023	C	`conf`	High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control. ISCAS Fangcen Zhong, Masanori Natsui, Takahiro Hanyu
2023	—	`conf`	Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware. ISMVL Ken Asano, Masanori Natsui, Takahiro Hanyu
2022	—	`conf`	Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator. MWSCAS Keisuke Sakamoto, Masanori Natsui, Takahiro Hanyu
2021	J	`jnl`	Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2020	—	`conf`	Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2019	J	`jnl`	A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2019	—	`conf`	An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2019	—	`conf`	Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks. ISMVL Tomoki Chiba, Masanori Natsui, Takahiro Hanyu
2018	J	`jnl`	Design of MTJ-Based nonvolatile logic gates for quantized neural networks. Microelectron. J. Masanori Natsui, Tomoki Chiba, Takahiro Hanyu
2018	—	`conf`	Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction. ISMVL Hiroki Suda, Masanori Natsui, Takahiro Hanyu
2017	A	`conf`	Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. DATE Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui
2016	—	`conf`	A study of a top-down error correction technique using Recurrent-Neural-Network-based learning. NEWCAS Masanori Natsui, Naoto Sugaya, Takahiro Hanyu
2016	—	`conf`	Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission. ISMVL Naoto Sugaya, Masanori Natsui, Takahiro Hanyu
2016	J	`jnl`	Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
2016	C	`conf`	Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2015	—	`conf`	Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2015	J	`jnl`	Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2015	A	`conf`	Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki
2015	—	`conf`	Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. ISMVL Takeaki Akutsu, Masanori Natsui, Takahiro Hanyu
2014	J	`jnl`	A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014	—	`conf`	Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI. NEWCAS Masanori Natsui, Takahiro Hanyu
2014	—	`conf`	Variation-Effect Analysis of MTJ-Based Multiple-Valued Programmable Resistors. ISMVL Masanori Natsui, Takahiro Hanyu
2013	—	`conf`	Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications. ISMVL Masanori Natsui, Kiyohiro Kashiuchi, Takahiro Hanyu
2013	J	`jnl`	Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices. J. Multiple Valued Log. Soft Comput. Masanori Natsui, Takahiro Hanyu
2013	J	`jnl`	Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electron. Express Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2013	C	`conf`	MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. ISCAS Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi
2013	—	`conf`	Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2012	—	`conf`	Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA. MWSCAS Daisuke Suzuki, Masanori Natsui, Takahiro Hanyu
2012	—	`conf`	Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2012	J	`jnl`	Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique. J. Multiple Valued Log. Soft Comput. Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu
2012	—	`conf`	Process-Variation-Resilient OTA Using MTJ-based Multi-level Resistance Control. ISMVL Masanori Natsui, Takaaki Nagashima, Takahiro Hanyu
2012	—	`conf`	Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system. NEWCAS Masanori Natsui, Takahiro Hanyu
2012	C	`conf`	Variation-resilient current-mode logic circuit design using MTJ devices. ISCAS YoungKeun Kim, Masanori Natsui, Takahiro Hanyu
2011	J	`jnl`	Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using IEICE Trans. Electron. Takayuki Konishi, Kenji Inazu, Jun Gyu Lee, Masanori Natsui, Shoichi Masui, Boris Murmann
2011	—	`conf`	Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme. ISMVL Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Takahiro Hanyu
2010	J	`jnl`	Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme. IEICE Trans. Inf. Syst. Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui, Takahiro Hanyu
2010	—	`conf`	Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control. ISMVL Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu
2009	—	`conf`	Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. ISMVL Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu
2008	—	`conf`	Automated Sizing of Analog Circuits based on Genetic Algorithm with Parameter Orthogonalization Procedure. ICINCO-ICSO Masanori Natsui, Yoshiaki Tadokoro
2007	J	`jnl`	Synthesis of current mirrors based on evolutionary graph generation with transmigration capability. IEICE Electron. Express Masanori Natsui, Yoshiaki Tadokoro, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2006	—	`conf`	GA-based approach to pitch recognition of musical consonance. ICINCO-SPSMC Masanori Natsui, Shunichi Kubo, Yoshiaki Tadokoro
2006	—	`conf`	Pitch estimation of difficult polyphony sounds overlapping some frequency components. ICINCO-SPSMC Yoshiaki Tadokoro, Masanori Natsui, Yasuhiro Seto, Michiru Yamaguchi
2005	J	`jnl`	Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis. J. Multiple Valued Log. Soft Comput. Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2004	A	`conf`	Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation. PPSN Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2003	B	`conf`	VLSI circuit design using an object-oriented framework of evolutionary graph generation system. IEEE Congress on Evolutionary Computation Naofumi Homma, Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
2002	J	`jnl`	Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
2002	—	`conf`	Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis. ISMVL Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
2001	—	`conf`	Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation. ISMVL Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi