Masanori Hayashikoshi

19 papers A 1C 2Journal 10Unranked 6
YearRankTypeTitle / Venue / Authors
2020 J jnl
An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors.
IEICE Trans. Inf. Syst.
Takashi Nakada, Hiroyuki Yanagihashi, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura
2019 J jnl
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications.
IEICE Trans. Electron.
Masanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka
2018 — conf
A Cost-Effective High Accuracy Auto-Trimming System without Tester Constraint for Low-End Embedded Flash Memory.
ISOCC
Junichi Suzuki, Junichi Yamashita, Masami Hanyu, Masamichi Ido, Tatsuya Saito, Yasuhiro Nakashima, Masanori Hayashikoshi, Yukiyoshi Kiyota
2018 J jnl
Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications.
IEEE Trans. Multi Scale Comput. Syst.
Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Yasumitsu Murai, Sugako Otani, Koji Nii, Yoshio Matsuda, Hiroyuki Kondo
2017 J jnl
An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation.
IEICE Trans. Inf. Syst.
Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
2017 C conf
Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors.
VLSI-SoC
Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Nakamura, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi
2017 — conf
Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications.
COOL Chips
Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Koji Nii, Hiroyuki Kondo
2016 C conf
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis.
VLSI-SoC
Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
2016 — conf
Low-power multi-sensor system with normally-off sensing technology for IoT applications.
ISOCC
Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Hiroyuki Kondo
2015 — conf
Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks.
DSDIS
Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura
2014 — conf
Data-aware power management for periodic real-time systems with non-volatile memory.
NVMSA
Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
2014 J jnl
Design Aid of Multi-core Embedded Systems with Energy Model.
Inf. Media Technol.
Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
2014 — conf
Normally-off MCU architecture for low-power sensor node.
ASP-DAC
Masanori Hayashikoshi, Yohei Sato, Hiroshi Ueki, Hiroyuki Kawai, Toru Shimizu
1993 J jnl
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters.
IEEE Des. Test Comput.
Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima
1992 J jnl
A 34-ns 16-Mb DRAM with controllable voltage down-converter.
IEEE J. Solid State Circuits
Hideto Hidaka, Kazutami Arimoto, Kazutoshi Hirayama, Masanori Hayashikoshi, Mikio Asakura, Masaki Tsukude, Tsukasa Oishi, Shinji Kawai, Katsuhiro Suma, Yasuhiro Konishi, Koji Tanaka, Wataru Wakamiya, Yoshikazu Ohno, Kazuyasu Fujishima
1992 A conf
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter.
ITC
Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima
1992 J jnl
A dual-mode sensing scheme of capacitor-coupled EEPROM cell.
IEEE J. Solid State Circuits
Masanori Hayashikoshi, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
1990 J jnl
A high-speed parallel sensing architecture for multi-megabit flash E
IEEE J. Solid State Circuits
Kiyoteru Kobayashi, Tatsuo Nakayama, Yoshikazu Miyawaki, Masanori Hayashikoshi, Yasushi Terada, Tsutomu Yoshihara
1989 J jnl
120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs.
IEEE J. Solid State Circuits
Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara