Masanori Hashimoto

268 papers A* 4A 27B 7C 11Misc 1Journal 109Unranked 109

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A Radiation-Hardened Self-Healing CMOS Imager with Online Pixel/Logic Annealing and Tile-Adaptive Compression for Space Applications. ISSCC Quan Cheng, Zhengke Yang, Haoyuan Li, Qiufeng Li, Zhen Kong, Gaoqiang Niu, Yuan Liang, Jiamin Li, Jerald Yoo, Masanori Hashimoto, Longyang Lin
2026	—	`conf`	FIawase: A SET Fault Injection Framework Towards Exhaustive System-Level Impact Evaluation. ASP-DAC Mingtao Zhang, Quan Cheng, Masanori Hashimoto
2026	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Hashimoto
2026	—	`conf`	Gundam: A Generalized Unified Design and Analysis Model for Matrix Multiplication on Edge. ASP-DAC Quan Cheng, Haoyuan Li, Weirong Dong, Mingqiang Huang, Longyang Lin, Masanori Hashimoto
2026	J	`jnl`	VeRA+: Vector-Based Lightweight Digital Compensation for Drift-Resilient RRAM In-Memory Computing. CoRR Weirong Dong, Kai Zhou, Zhen Kong, Zhengke Yang, Quan Cheng, Haoyuan Li, Junkai Huang, Jun Lan, Yida Li, Masanori Hashimoto, Longyang Lin
2025	—	`conf`	A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-on-Chip Towards In-Orbit Computing. CICC Quan Cheng, Qiufeng Li, Weirong Dong, Mingtao Zhang, Ruilin Zhang, Mingqiang Huang, Hao Yu, Yiyu Shi, Hiromitsu Awano, Takashi Sato, Longyang Lin, Masanori Hashimoto
2025	J	`jnl`	A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement. CoRR Yuibi Gomi, Akira Sato, Waleed Madany, Kenichi Okada, Satoshi Adachi, Masatoshi Itoh, Masanori Hashimoto
2025	J	`jnl`	A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement. IEEE Solid State Circuits Lett. Yuibi Gomi, Akira Sato, Waleed Madany, Kenichi Okada, Satoshi Adachi, Masatoshi Itoh, Masanori Hashimoto
2025	J	`jnl`	A Hardware-Aware Failure-Detection Method for GPU Control-Logic. IEEE Access Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Kojiro Ito, Masanori Hashimoto
2025	A	`conf`	A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators : - Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation -. ISLPED Quan Cheng, Huizi Zhang, Qiufeng Li, Yuan Liang, Mingtao Zhang, Zhenzhe Chen, Ruilin Zhang, Jinjun Xiong, Mingqiang Huang, Longyang Lin, Masanori Hashimoto
2025	J	`jnl`	An 88.5 fs IEEE Trans. Circuits Syst. I Regul. Pap. Yuan Liang, Wen Jin, Zhongyuan Fang, Quan Cheng, Masanori Hashimoto
2025	J	`jnl`	Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Moxiao Lou, Jin Wang, Humiao Li, Zhengke Yang, Quan Cheng, Jiamin Li, Masanori Hashimoto, Longyang Lin
2025	J	`jnl`	Efficient Calibration for RRAM-based In-Memory Computing using DoRA. CoRR Weirong Dong, Kai Zhou, Zhen Kong, Quan Cheng, Junkai Huang, Zhengke Yang, Masanori Hashimoto, Longyang Lin
2025	A	`conf`	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis. ITC Quan Cheng, Hao-Yang Chi, Chien-Hsing Liang, Yu-Hong Chao, Huizi Zhang, Yuan Liang, Mingtao Zhang, Wang Liao, Jinjun Xiong, Jing-Jia Liou, Masanori Hashimoto, Longyang Lin
2025	A	`conf`	HachiFI: A Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation. DATE Quan Cheng, Wang Liao, Ruilin Zhang, Hao Yu, Longyang Lin, Masanori Hashimoto
2025	—	`conf`	Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications. ASP-DAC Tomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto
2025	—	`conf`	High-Clarity Underwater 3D Display Enabled by Electrolysis-Free Water-Mediated Wireless Power Transmission. SIGGRAPH Asia Posters Chiaki Takahashi, Hayato Sawada, Ryo Shirai, Masanori Hashimoto
2025	J	`jnl`	In-Situ Hardware Error Detection Using Specification-Derived Petri Net Models and Behavior-Derived State Sequences. CoRR Tomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto
2025	—	`conf`	ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges. ASP-DAC Masanori Hashimoto, Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi
2025	A	`conf`	Tenpura: A General Transient Fault Evaluation and Scope Narrowing Platform for Ultra-fast Reliability Analysis. ICCAD Quan Cheng, Huizi Zhang, Chien-Hsing Liang, Mingtao Zhang, Jing-Jia Liou, Jinjun Xiong, Longyang Lin, Masanori Hashimoto
2025	—	`conf`	UAV Path Planning for Finding Persons in Need of Rescue After the Disaster. NBiS (1) Masanori Hashimoto, Takahiro Uchiya
2025	—	`conf`	Window Function-Less DFT with Reduced Noise and Latency for Real-Time Music Analysis. EUSIPCO Cai Biesinger, Hiromitsu Awano, Masanori Hashimoto
2024	—	`conf`	A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping. A-SSCC Quan Cheng, Longyang Lin, Mingqiang Huang, Qiufeng Li, Zhengke Yang, Liuyao Dai, Hao Yu, Yu-Jen Chen, Yiyu Shi, Masanori Hashimoto
2024	—	`conf`	An SEU Cross Section Model Reproducing LET and Voltage Dependence in Bulk Planar and FinFET SRAMs. IRPS Kozo Takeuchi, Takashi Kato, Masanori Hashimoto
2024	J	`jnl`	Analytical Equivalent Circuit Extraction of Foreign Metal Objects in WPT Systems. IEEE Access Ryo Shirai, Goro Nakao, Masanori Hashimoto
2024	—	`conf`	Development of Tiny Wireless Position Tracker Enabling Real-Time Intuitive 3D Modeling. SIGGRAPH Asia Posters Yuki Maegawa, Masanori Hashimoto, Ryo Shirai
2024	A*	`conf`	How accurately can soft error impact be estimated in black-box/white-box cases? - a case study with an edge AI SoC -. DAC Quan Cheng, Qiufeng Li, Longyang Lin, Wang Liao, Liuyao Dai, Hao Yu, Masanori Hashimoto
2024	B	`conf`	Logic Locking over TFHE for Securing User Data and Algorithms. ASPDAC Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto
2024	C	`conf`	S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators. ICCD Mingtao Zhang, Quan Cheng, Hiromitsu Awano, Longyang Lin, Masanori Hashimoto
2023	J	`jnl`	A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier. IEEE Trans. Circuits Syst. II Express Briefs Quan Cheng, Liuyao Dai, Mingqiang Huang, Ao Shen, Wei Mao, Masanori Hashimoto, Hao Yu
2023	C	`conf`	Avoiding Soft Error-Induced Illegal Memory Accesses in GPU with Inter-Thread Communication. IOLTS Riku Iwamoto, Masanori Hashimoto
2023	J	`jnl`	B2N2: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA. Integr. Hiromitsu Awano, Masanori Hashimoto
2023	—	`conf`	Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons. IRPS Kazusa Takami, Yuibi Gomi, Shin-ichiro Abe, Wang Liao, Seiya Manabe, Tetsuro Matsumoto, Masanori Hashimoto
2023	—	`conf`	Performance comparison of memristor crossbar-based analog and FPGA-based digital weight-memory-less neural networks. ICRC Chinamu Kawano, Masanori Hashimoto
2023	J	`jnl`	Recurrent Residual Networks Contain Stronger Lottery Tickets. IEEE Access Ángel López García-Arias, Yasuyuki Okoshi, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
2023	J	`jnl`	Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Quan Cheng, Mingqiang Huang, Changhai Man, Ao Shen, Liuyao Dai, Hao Yu, Masanori Hashimoto
2023	—	`conf`	Toward Instant 3D Modeling: Highly Parallelizable Shape Reproduction Method for Soft Object Containing Numerous Tiny Position Trackers. IUI Companion Minoru Harimaya, Ryo Shirai, Masanori Hashimoto
2023	J	`jnl`	Vulnerability Estimation of DNN Model Parameters with Few Fault Injections. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yangchao Zhang, Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Masanori Hashimoto
2022	J	`jnl`	A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. IEICE Trans. Inf. Syst. Dehua Liang, Jun Shiomi, Noriyuki Miura, Masanori Hashimoto, Hiromitsu Awano
2022	J	`jnl`	Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taiyu Cheng, Yutaka Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto
2022	—	`conf`	DC Magnetic Field-Based Analytical Localization Robust to Known Stationary Magnetic Object. MWSCAS Toshihisa Tanaka, Ryo Shirai, Masanori Hashimoto
2022	A	`conf`	Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections. DATE Yangchao Zhang, Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Masanori Hashimoto
2022	—	`conf`	Investigating Small Device Implementation of FRET-based Optical Reservoir Computing. MWSCAS Masafumi Tanakal, Jaehoon Yu, Masaki Nakagawa, Naoya Tate, Masanori Hashimoto
2022	J	`jnl`	Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yutaka Masuda, Jun Nagayama, Taiyu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
2022	—	`conf`	Shape-Flexible Underwater Display System with Wirelessly Powered and Controlled Smart LEDs. IUI Companion Ryo Shirai, Masanori Hashimoto
2022	J	`jnl`	Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation. IEEE J. Solid State Circuits Xu Bai, Naoki Banno, Makoto Miyamura, Ryusuke Nebashi, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
2022	J	`jnl`	VirtualSync+: Timing Optimization With Virtual Synchronization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann
2022	J	`jnl`	VirtualSync+: Timing Optimization with Virtual Synchronization. CoRR Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann
2021	A	`conf`	BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter. DATE Dehua Liang, Masanori Hashimoto, Hiromitsu Awano
2021	A	`conf`	Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. DATE Yutaka Masuda, Jun Nagayama, Taiyu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
2021	A	`conf`	Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. BMVC Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
2021	J	`jnl`	Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. CoRR Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
2021	A	`conf`	MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. DATE Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi
2021	J	`jnl`	Make it Trackable: An Instant Magnetic Tracking System With Coil-Free Tiny Trackers. IEEE Access Ryo Shirai, Yuichi Itoh, Masanori Hashimoto
2021	C	`conf`	Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling. ISCAS Taiyu Cheng, Masanori Hashimoto
2021	—	`conf`	Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization. ASP-DAC Taiyu Cheng, Yukata Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto
2021	—	`conf`	Submarine LED: Wirelessly powered underwater display controlling its buoyancy. SIGGRAPH ASIA Posters Ryo Shirai, Masanori Hashimoto
2020	—	`conf`	33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
2020	J	`jnl`	A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto
2020	A	`conf`	BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA. DATE Hiromitsu Awano, Masanori Hashimoto
2020	—	`conf`	Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs. IRPS Wang Liao, Kojiro Ito, Yukio Mitsuyama, Masanori Hashimoto
2020	A	`conf`	Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing. ITC Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Kojiro Ito, Masanori Hashimoto
2020	A	`conf`	Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA. DATE Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto
2020	—	`conf`	Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets. IRPS Shin-ichiro Abe, Tatsuhiko Sato, Junya Kuroda, Seiya Manabe, Yukinobu Watanabe, Wang Liao, Kojiro Ito, Masanori Hashimoto, Masahide Harada, Kenichi Oikawa, Yasuhiro Miyake
2020	J	`jnl`	Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training. Integr. Taiyu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto
2020	C	`conf`	Low-Cost Reservoir Computing using Cellular Automata and Random Forests. ISCAS Ángel López García-Arias, Jaehoon Yu, Masanori Hashimoto
2020	—	`conf`	Memory Efficient Training using Lookup-Table-based Quantization for Neural Network. AICAS Kazuki Onishi, Jaehoon Yu, Masanori Hashimoto
2020	—	`conf`	Position and Posture Estimation of Capsule Endoscopy with a Single Wearable Coil Toward Daily Life Diagnosis. MWSCAS Ryohei Shimizu, Ryo Shirai, Masanori Hashimoto
2020	A	`conf`	Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction. ITC Jun Chen, Masanori Hashimoto
2020	J	`jnl`	Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto
2020	—	`conf`	Soft Error and Its Countermeasures in Terrestrial Environment. ASP-DAC Masanori Hashimoto, Wang Liao
2020	—	`conf`	When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. ASP-DAC Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo
2019	J	`jnl`	Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate. IEICE Trans. Electron. Wang Liao, Masanori Hashimoto
2019	J	`jnl`	Characterizing SRAM and FF soft error rates with measurement and simulation. Integr. Masanori Hashimoto, Kazutoshi Kobayashi, Jun Furuta, Shin-ichiro Abe, Yukinobu Watanabe
2019	—	`conf`	Coverage-scalable instant tabletop positioning system with self-localizable anchor nodes. IUI Companion Pei Hao Chen, Ryo Shirai, Masanori Hashimoto
2019	—	`conf`	Distilling Knowledge for Non-Neural Networks. APSIPA Shota Fukui, Jaehoon Yu, Masanori Hashimoto
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019	J	`jnl`	MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yutaka Masuda, Masanori Hashimoto
2019	—	`conf`	Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier. PATMOS Taiyu Cheng, Jaehoon Yu, Masanori Hashimoto
2019	—	`conf`	Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs. IRPS Wang Liao, Masanori Hashimoto, Seiya Manabe, Yukinobu Watanabe, Shin-ichiro Abe, Keita Nakano, Hayato Takeshita, Motonobu Tampo, Soshi Takeshita, Yasuhiro Miyake
2019	J	`jnl`	Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takahiro Nakayama, Masanori Hashimoto
2019	—	`conf`	Training Data Reduction using Support Vectors for Neural Networks. APSIPA Toranosuke Tanio, Kouya Takeda, Jaehoon Yu, Masanori Hashimoto
2019	J	`jnl`	When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. CoRR Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo
2018	—	`conf`	A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes. NEWCAS Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto
2018	J	`jnl`	Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving. IEEE Trans. Very Large Scale Integr. Syst. Yutaka Masuda, Takao Onoye, Masanori Hashimoto
2018	J	`jnl`	An analytic evaluation on soft error immunity enhancement due to temporal triplication. Int. J. Embed. Syst. Ryutaro Doi, Masanori Hashimoto, Takao Onoye
2018	A	`conf`	Comparing voltage adaptation performance between replica and in-situ timing monitors. ICCAD Yutaka Masuda, Jun Nagayama, Hirotaka Takeno, Yoshimasa Ogawa, Yoichi Momiyama, Masanori Hashimoto
2018	J	`jnl`	From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era. IPSJ Trans. Syst. LSI Des. Methodol. Bing Li, Masanori Hashimoto, Ulf Schlichtmann
2018	—	`conf`	Hardware Architecture for Fast General Object Detection using Aggregated Channel Features. A-SSCC Koichi Mitsunari, Jaehoon Yu, Masanori Hashimoto
2018	J	`jnl`	Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Masanori Hashimoto
2018	—	`conf`	Hold violation analysis for functional test of ultra-low temperature circuits at room temperature. VLSI-DAT Takahiro Nakayama, Masanori Hashimoto
2018	—	`conf`	Interconnect Delay Analysis for RRAM Crossbar Based FPGA. ISVLSI Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu
2018	—	`conf`	MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits. ASP-DAC Yutaka Masuda, Masanori Hashimoto
2018	—	`conf`	Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties. ISQED Kuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li
2018	—	`conf`	SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA. ISVLSI Ryutaro Doi, Masanori Hashimoto
2018	J	`jnl`	Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto
2018	A	`conf`	Sneak path free reconfiguration of via-switch crossbars based FPGA. ICCAD Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto
2018	J	`jnl`	Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
2018	A*	`conf`	Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. DAC Grace Li Zhang, Bing Li, Masanori Hashimoto, Ulf Schlichtmann
2017	—	`conf`	Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V -. NEWCAS Wang Liao, Soichi Hirokawa, Ryo Harada, Masanori Hashimoto
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	A	`conf`	GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction. IUI Kauzki Hirosue, Shohei Ukawa, Yuichi Itoh, Takao Onoye, Masanori Hashimoto
2017	J	`jnl`	Minimizing detection-to-boosting latency toward low-power error-resilient circuits. Integr. Chih-Cheng Hsu, Masanori Hashimoto, Mark Po-Hung Lin
2017	C	`conf`	Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node. ISCAS Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto
2017	B	`conf`	Near-future traffic evaluation based navigation for automated driving vehicles. Intelligent Vehicles Symposium Kuen-Wey Lin, Yih-Lang Li, Masanori Hashimoto
2017	J	`jnl`	Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yutaka Masuda, Takao Onoye, Masanori Hashimoto
2017	—	`conf`	Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes. ASICON Masanori Hashimoto, Ryo Shirai, Yuichi Itoh, Tetsuya Hirose
2016	B	`conf`	A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto
2016	A	`conf`	Critical path isolation for time-to-failure extension and lower voltage operation. ICCAD Yutaka Masuda, Masanori Hashimoto, Takao Onoye
2016	C	`conf`	Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms. IOLTS Yutaka Masuda, Masanori Hashimoto, Takao Onoye
2016	—	`conf`	Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits. SLIP Chih-Cheng Hsu, Mark Po-Hung Lin, Masanori Hashimoto
2016	—	`conf`	Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. ASP-DAC Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li
2015	A*	`conf`	3D node localization from node-to-node distance information using cross-entropy method. VR Shohei Ukawa, Tatsuya Shinada, Masanori Hashimoto, Yuichi Itoh, Takao Onoye
2015	—	`conf`	An oscillator-based true random number generator with process and temperature tolerance. ASP-DAC Takehiko Amaki, Masanori Hashimoto, Takao Onoye
2015	—	`conf`	Area efficient device-parameter estimation using sensitivity-configurable ring oscillator. ASP-DAC Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye
2015	J	`jnl`	Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye
2015	—	`conf`	Impact of package on neutron induced single event upset in 20 nm SRAM. IRPS Taiki Uemura, Takashi Kato, Hideya Matsuyama, Masanori Hashimoto
2015	—	`conf`	Investigation of single event upset and total ionizing dose in FeRAM for medical electronic tag. IRPS Taiki Uemura, Masanori Hashimoto
2015	J	`jnl`	Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daisuke Fukuda, Kenichi Watanabe, Yuji Kanazawa, Masanori Hashimoto
2015	A	`conf`	Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise. ICCAD Yutaka Masuda, Masanori Hashimoto, Takao Onoye
2015	C	`conf`	Real-time on-chip supply voltage sensor and its application to trace-based timing error localization. IOLTS Miho Ueno, Masanori Hashimoto, Takao Onoye
2015	—	`conf`	Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera
2015	—	`conf`	Soft error immune latch design for 20 nm bulk CMOS. IRPS Taiki Uemura, Takashi Kato, Hideya Matsuyama, Masanori Hashimoto
2015	A	`conf`	Stochastic timing error rate estimation under process and temporal variations. ITC Shoichi Iizuka, Yutaka Masuda, Masanori Hashimoto, Takao Onoye
2014	J	`jnl`	A Process and Temperature Tolerant Oscillator-Based True Random Number Generator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takehiko Amaki, Masanori Hashimoto, Takao Onoye
2014	J	`jnl`	Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Konoura, Takashi Imagawa, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2014	J	`jnl`	Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daisuke Fukuda, Kenichi Watanabe, Naoki Idani, Yuji Kanazawa, Masanori Hashimoto
2014	J	`jnl`	NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Konoura, Toshihiro Kameda, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2014	—	`conf`	Opportunities and Verification Challenges of Run-Time Performance Adaptation. ATS Masanori Hashimoto
2014	J	`jnl`	Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera
2014	J	`jnl`	SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2014	—	`conf`	Stochastic verification of run-time performance adaptation with field delay testing. APCCAS Masanori Hashimoto
2013	J	`jnl`	A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation. IEICE Electron. Express Igors Homjakovs, Tetsuya Hirose, Yuji Osaki, Masanori Hashimoto, Takao Onoye
2013	J	`jnl`	A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling. IEEE Trans. Inf. Forensics Secur. Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2013	J	`jnl`	A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations. Integr. Kenichi Shinkai, Masanori Hashimoto, Takao Onoye
2013	B	`conf`	Extracting device-parameter variations using a single sensitivity-configurable ring oscillator. ETS Yuma Higuchi, Kenichi Shinkai, Masanori Hashimoto, Rahul M. Rao, Sani R. Nassif
2013	J	`jnl`	Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices. IEICE Trans. Inf. Syst. Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2013	J	`jnl`	Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture. IEEE Trans. Very Large Scale Integr. Syst. Dawood Alnajiar, Hiroaki Konoura, Younghun Ko, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2013	J	`jnl`	Jitter Amplifier for Oscillator-Based True Random Number Generator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takehiko Amaki, Masanori Hashimoto, Takao Onoye
2013	—	`conf`	Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. ReConFig Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye
2013	J	`jnl`	PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices. IEICE Electron. Express Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2013	—	`conf`	Proximity distance estimation based on capacitive coupling between 1mm NEWCAS Tatsuya Shinada, Masanori Hashimoto, Takao Onoye
2013	—	`conf`	Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures. IPDPS Workshops Miho Ueno, Masanori Hashimoto, Takao Onoye
2013	J	`jnl`	Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Igors Homjakovs, Masanori Hashimoto, Tetsuya Hirose, Takao Onoye
2013	—	`conf`	Soft error immunity of subthreshold SRAM. ASICON Masanori Hashimoto
2013	A	`conf`	Stochastic error rate estimation for adaptive speed control with field delay testing. ICCAD Shoichi Iizuka, Masafumi Mizuno, Dan Kuroda, Masanori Hashimoto, Takao Onoye
2013	J	`jnl`	Supply Noise Suppression by Triple-Well Structure. IEEE Trans. Very Large Scale Integr. Syst. Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye
2012	J	`jnl`	A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shuta Kimura, Masanori Hashimoto, Takao Onoye
2012	B	`conf`	A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture. FPL Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2012	J	`jnl`	Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2012	—	`conf`	Body bias clustering for low test-cost post-silicon tuning. ASP-DAC Shuta Kimura, Masanori Hashimoto, Takao Onoye
2012	J	`jnl`	Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Enami, Takashi Sato, Masanori Hashimoto
2012	J	`jnl`	Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasumichi Takai, Masanori Hashimoto, Takao Onoye
2012	—	`conf`	Signal-dependent analog-to-digital converter based on MINIMAX sampling. ISOCC Igors Homjakovs, Masanori Hashimoto, Takao Onoye, Tetsuya Hirose
2012	—	`conf`	Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices. ReConFig Dawood Alnajiar, Masanori Hashimoto, Takao Onoye, Yukio Mitsuyama
2011	J	`jnl`	An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion. IEEE Trans. Circuits Syst. II Express Briefs Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye
2011	C	`conf`	An oscillator-based true random number generator with jitter amplifier. ISCAS Takehiko Amaki, Masanori Hashimoto, Takao Onoye
2011	—	`conf`	Device-parameter estimation with on-chip variation sensors considering random variability. ASP-DAC Kenichi Shinkai, Masanori Hashimoto
2011	J	`jnl`	Extracting Device-Parameter Variations with RO-Based Sensors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kenichi Shinkai, Masanori Hashimoto, Takao Onoye
2011	B	`conf`	Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures. FPL Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2011	—	`conf`	Jitter amplifier for oscillator-based true random number generator. ASP-DAC Takehiko Amaki, Masanori Hashimoto, Takao Onoye
2011	—	`conf`	NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode. PATMOS Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2011	—	`conf`	Power gating implementation for noise mitigation with body-tied triple-well structure. CICC Yasumichi Takai, Masanori Hashimoto, Takao Onoye
2011	—	`conf`	Run-time adaptive performance compensation using on-chip sensors. ASP-DAC Masanori Hashimoto
2011	J	`jnl`	Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takaaki Okumura, Masanori Hashimoto
2011	J	`jnl`	Stress Probability Computation for Estimating NBTI-Induced Delay Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2010	Misc	`conf`	A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling. WISA Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2010	J	`jnl`	Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinyu Ninomiya, Masanori Hashimoto
2010	—	`conf`	Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. ASP-DAC Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2010	—	`conf`	Clock skew reduction by self-compensating manufacturing variability with on-chip sensors. ACM Great Lakes Symposium on VLSI Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, Takao Onoye
2010	—	`conf`	Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. ISQED Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2010	J	`jnl`	Gate Delay Estimation in STA under Dynamic Power Supply Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto
2010	—	`conf`	Gate delay estimation in STA under dynamic power supply noise. ASP-DAC Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto
2010	J	`jnl`	Impact of Self-Heating in Wire Interconnection on Timing. IEICE Trans. Electron. Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto
2010	J	`jnl`	Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2010	—	`conf`	Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. ISQED Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2010	J	`jnl`	Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue
2010	J	`jnl`	Prediction of Self-Heating in Short Intra-Block Wires. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kenichi Shinkai, Masanori Hashimoto, Takao Onoye
2010	—	`conf`	Setup time, hold time and clock-to-Q delay computation under dynamic supply noise. CICC Takaaki Okumura, Masanori Hashimoto
2010	J	`jnl`	Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Enami, Shinyu Ninomiya, Kenichi Shinkai, Shinya Abe, Masanori Hashimoto
2010	J	`jnl`	Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	—	`conf`	A case for exploiting complex arithmetic circuits towards performance yield enhancement. ISQED Shingo Watanabe, Masanori Hashimoto, Toshinori Sato
2009	—	`conf`	Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. CICC Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	J	`jnl`	All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform. IEEE J. Solid State Circuits Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye
2009	J	`jnl`	An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto
2009	J	`jnl`	An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. IEICE Trans. Electron. Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	B	`conf`	Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye
2009	—	`conf`	Enhancement of grid-based spatially-correlated variability modeling for improving SSTA accuracy. SoCC Shinyu Ninomiya, Masanori Hashimoto
2009	—	`conf`	High performance on-chip differential signaling using passive compensation for global communication. ASP-DAC Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng
2009	J	`jnl`	Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato
2009	J	`jnl`	Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto
2009	J	`jnl`	Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	—	`conf`	Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ASP-DAC Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2009	A	`conf`	Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. ISLPED Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2008	J	`jnl`	Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng
2008	J	`jnl`	Area-Efficient Reconfigurable Architecture for Media Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa
2008	—	`conf`	Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. ISQED Shinya Abe, Masanori Hashimoto, Takao Onoye
2008	J	`jnl`	Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinya Abe, Masanori Hashimoto, Takao Onoye
2008	A	`conf`	Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2008	A	`conf`	Decoupling capacitance allocation for timing with statistical noise model and timing analysis. ICCAD Takashi Enami, Masanori Hashimoto, Takashi Sato
2008	—	`conf`	Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification. ASP-DAC Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye
2008	—	`conf`	Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
2008	—	`conf`	High performance current-mode differential logic. ASP-DAC Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto
2008	J	`jnl`	Impact of Well Edge Proximity Effect on Timing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto
2008	J	`jnl`	Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects. IEEE J. Solid State Circuits Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye
2008	C	`conf`	On-chip high performance signaling using passive compensation. ICCD Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng
2008	—	`conf`	Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise. ISPD Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto
2008	J	`jnl`	Timing Analysis Considering Temporal Supply Voltage Fluctuation. IEICE Trans. Inf. Syst. Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera
2007	—	`conf`	Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration. CICC Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng
2007	—	`conf`	Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect. CICC Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye
2007	—	`conf`	Future Prediction of Self-Heating in Short Intra-Block Wires. ISQED Kenichi Shinkai, Masanori Hashimoto, Takao Onoye
2007	—	`conf`	Impact of well edge proximity effect on timing. ESSCIRC Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto
2007	J	`jnl`	Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling. IEICE Trans. Electron. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2007	J	`jnl`	Proposal of Metrics for SSTA Accuracy Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroyuki Kobayashi, Nobuto Ono, Takashi Sato, Jiro Iwai, Hidenari Nakashima, Takaaki Okumura, Masanori Hashimoto
2007	J	`jnl`	Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye
2007	J	`jnl`	Timing Analysis Considering Spatial Power/Ground Level Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera
2007	J	`jnl`	Transistor Sizing of LCD Driver Circuit for Technology Migration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa
2007	J	`jnl`	Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement. IEEE Trans. Circuits Syst. II Express Briefs Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye
2006	J	`jnl`	A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa
2006	A	`conf`	A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. ICCAD Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye
2006	J	`jnl`	Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto
2006	J	`jnl`	Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2006	—	`conf`	Interconnect RL extraction at a single representative frequency. ASP-DAC Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2006	—	`conf`	Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects. CICC Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye
2006	—	`conf`	Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation. CICC Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye
2006	J	`jnl`	On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Sato, Junji Ichimiya, Nobuto Ono, Masanori Hashimoto
2006	C	`conf`	Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. ICCD Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye
2006	J	`jnl`	Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
2005	J	`jnl`	A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL. IEICE Trans. Electron. Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera
2005	—	`conf`	A design scheme for sampling switch in active matrix LCD. ECCTD Shingo Takahashi, Akira Taji, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa
2005	—	`conf`	Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. ASP-DAC Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera
2005	—	`conf`	Design guideline for resistive termination of on-chip high-speed interconnects. CICC Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2005	J	`jnl`	Effects of On-Chip Inductance on Power Distribution Grid. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
2005	—	`conf`	Effects of on-chip inductance on power distribution grid. ISPD Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
2005	—	`conf`	Interconnect capacitance extraction for system LCD circuits. ACM Great Lakes Symposium on VLSI Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa
2005	—	`conf`	Measurement and analysis of delay variation due to inductive coupling. CICC Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye
2005	J	`jnl`	On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto
2005	—	`conf`	On-chip thermal gradient analysis and temperature flattening for SoC design. ASP-DAC Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto
2005	J	`jnl`	Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2005	—	`conf`	Return path selection for loop RL extraction. ASP-DAC Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2005	J	`jnl`	Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda
2005	—	`conf`	Statistical Analysis of Clock Skew Variation in H-Tree Structure. ISQED Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera
2005	J	`jnl`	Statistical Analysis of Clock Skew Variation in H-Tree Structure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera
2005	J	`jnl`	Successive Pad Assignment for Minimizing Supply Voltage Drop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
2005	—	`conf`	Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. ASP-DAC Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
2005	—	`conf`	Timing analysis considering temporal supply voltage fluctuation. ASP-DAC Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera
2004	—	`conf`	A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. ASP-DAC Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera
2004	—	`conf`	Automatic Generation of Standard Cell Library in VDSM Technologies. ISQED Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera
2004	J	`jnl`	Equivalent waveform propagation for static timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
2004	—	`conf`	Performance limitation of on-chip global interconnects for high-speed signaling. CICC Akira Tsuchiya, Yuuya Gotoh, Masanori Hashimoto, Hidetoshi Onodera
2004	—	`conf`	Representative frequency for interconnect R(f)L(f)C extraction. ASP-DAC Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2004	A	`conf`	Timing analysis considering spatial power/ground level variation. ICCAD Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera
2003	—	`conf`	Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. ASP-DAC Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto
2003	—	`conf`	Capturing crosstalk-induced waveform for accurate static timing analysis. ISPD Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
2003	J	`jnl`	Crosstalk Noise Estimation for Generic RC Trees. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera
2003	A	`conf`	Equivalent Waveform Propagation for Static Timing Analysis. ICCAD Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
2003	J	`jnl`	Experimental Study on Cell-Base High-Performance Datapath Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Hashimoto, Yoshiteru Hayashi, Hidetoshi Onodera
2003	J	`jnl`	Representative Frequency for Interconnect R(f)L(f)C Extraction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2003	—	`conf`	Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies. ASP-DAC Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera
2002	—	`conf`	Crosstalk noise optimization by post-layout transistor sizing. ISPD Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera
2002	—	`conf`	Experimental Study on Cell-Base High-Performance Datapath Design. IWLS Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera
2002	J	`jnl`	Increase in Delay Uncertainty by Performance Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Hashimoto, Hidetoshi Onodera
2001	C	`conf`	Crosstalk Noise Estimation for Generic RC Trees. ICCD Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera
2001	—	`conf`	Increase in delay uncertainty by performance optimization. ISCAS (5) Masanori Hashimoto, Hidetoshi Onodeva
2001	—	`conf`	Post-layout transistor sizing for power reduction in cell-based design. ASP-DAC Masanori Hashimoto, Hidetoshi Onodera
2000	—	`conf`	A performance optimization method by gate sizing using statistical static timing analysis. ISPD Masanori Hashimoto, Hidetoshi Onodera
1999	A*	`conf`	A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
1998	A	`conf`	A power optimization method considering glitch reduction by gate sizing. ISLPED Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru