Masanori Hariyama

101 papers A* 2A 3C 7Misc 1Journal 53Unranked 34

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Exploring Spatial and Temporal Parallelism for Vision Transformer Acceleration. MCSoC Hasitha Muthumala Waidyasooriya, Tomohiro Matsui, Daisuke Tanaka, Masanori Hariyama
2025	—	`conf`	Fpga-Based Highly Parallel Architecture for Multi-Robot Path Planning. MCSoC Kosei Nishio, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2025	—	`conf`	Large-Scale AGV Routing Based on Multi-FPGA SQA Acceleration. ASP-DAC Thinh NguyenQuang, Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki
2024	J	`jnl`	Performance evaluation of Word2vec accelerators exploiting spatial and temporal parallelism on DDR/HBM-based FPGAs. J. Supercomput. Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2022	J	`jnl`	A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory. IEEE Access Hasitha Muthumala Waidyasooriya, Hiroki Oshiyama, Yuya Kurebayashi, Masanori Hariyama, Masayuki Ohzeki
2022	J	`jnl`	Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators. J. Supercomput. Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2022	J	`jnl`	FPGA-Accelerated Searchable Encrypted Database Management Systems for Cloud Services. IEEE Trans. Cloud Comput. Mitsuhiro Okada, Takayuki Suzuki, Naoya Nishio, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2022	—	`conf`	FPGA-Based Prototype of a Quantum Annealing Simulator for Sparse Ising Model. MCSoC Hasitha Muthumala Waidyasooriya, Yuta Ohma, Masanori Hariyama
2022	—	`conf`	Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++. MWSCAS Kosiro Obata, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2022	—	`conf`	OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. MWSCAS Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano
2022	J	`jnl`	Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU. J. Supercomput. Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2022	C	`conf`	Word2Vec FPGA Accelerator Based on Spatial and Temporal Parallelism. PDCAT Hasitha Muthumala Waidyasooriya, Shutaro Ishihara, Masanori Hariyama
2021	J	`jnl`	Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing. IEEE Trans. Emerg. Top. Comput. Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2020	J	`jnl`	A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism. IEEE Access Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2020	J	`jnl`	An FPGA accelerator for PatchMatch multi-view stereo using OpenCL. J. Real Time Image Process. Shunsuke Tatsumi, Masanori Hariyama, Koichi Ito, Takafumi Aoki
2020	Misc	`conf`	Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories. SAC Chia-Yin Liu, Yi-Jung Chen, Masanori Hariyama
2019	—	`conf`	A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA. CANDAR Workshops Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Taisuke Ono, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa
2019	—	`conf`	Benchmarks for FPGA-Targeted High-Level-Synthesis. CANDAR Hasitha Muthumala Waidyasooriya, Yasuaki Iimura, Masanori Hariyama
2019	—	`conf`	Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation. CANDAR Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2019	C	`conf`	FPGA-Based Acceleration of Word2vec using OpenCL. ISCAS Taisuke Ono, Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa
2019	J	`jnl`	Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability. IEEE Access Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2019	J	`jnl`	OpenCL-based design of an FPGA accelerator for quantum annealing simulation. J. Supercomput. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masamichi J. Miyama, Masayuki Ohzeki
2018	—	`conf`	A System for Estimating Optimal Resected Liver Regions Considering Practical Surgical Constraints. ISPACS Yaya Watanabe, Masanori Hariyama, Mitsugi Shimoda
2018	—	`conf`	Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL. ISPACS Hasitha Muthumala Waidyasooriya, Yusuke Araki, Masanori Hariyama
2018	—	`ch.`	Advanced Devices and Architectures. Principles and Structures of FPGAs Masato Motomura, Masanori Hariyama, Minoru Watanabe
2018	—	`conf`	Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems. SCFA Yuki Hiradate, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masaaki Harada
2017	J	`jnl`	An FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL. Int. J. Networked Distributed Comput. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
2017	C	`conf`	Architecture of an FPGA accelerator for LDA-based inference. SNPD Taisuke Ono, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tsukasa Ishigaki
2017	J	`jnl`	OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions. Int. J. Reconfigurable Comput. Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera
2017	J	`jnl`	OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology. IEEE Trans. Parallel Distributed Syst. Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Shunsuke Tatsumi, Masanori Hariyama
2016	C	`conf`	Architecture of an FPGA accelerator for molecular dynamics simulation using OpenCL. ICIS Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
2016	J	`jnl`	Evaluation of an OpenCL-Based FPGA Platform for Particle Filter. J. Adv. Comput. Intell. Intell. Informatics Shunsuke Tatsumi, Masanori Hariyama, Norikazu Ikoma
2016	C	`conf`	FPGA-based deep-pipelined architecture for FDTD acceleration using OpenCL. ICIS Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2016	J	`jnl`	Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform. IEEE Trans. Parallel Distributed Syst. Hasitha Muthumala Waidyasooriya, Masanori Hariyama
2015	J	`jnl`	Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path. IEEE Trans. Very Large Scale Integr. Syst. Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
2015	J	`jnl`	Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2015	—	`conf`	Hardware-oriented succinct-data-structure based on block-size-constrained compression. SoCPaR Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama
2014	—	`conf`	Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing. APCCAS Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama
2014	J	`jnl`	FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation. J. Comput. Eng. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, Michitaka Kameyama
2013	J	`jnl`	Architecture of an Asynchronous FPGA for Handshake-Component-Based Design. IEICE Trans. Inf. Syst. Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
2013	J	`jnl`	Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2013	J	`jnl`	Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures. J. Multiple Valued Log. Soft Comput. Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
2013	—	`conf`	Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment. EMBC Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2012	J	`jnl`	Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. IEICE Trans. Electron. Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama
2012	J	`jnl`	Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. IEICE Trans. Electron. Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2012	C	`conf`	Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. ISCAS Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2012	C	`conf`	FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. ISCAS Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
2012	J	`jnl`	Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
2011	J	`jnl`	A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. IEEE Trans. Very Large Scale Integr. Syst. Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2011	J	`jnl`	A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals? J. Multiple Valued Log. Soft Comput. Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama
2011	—	`conf`	An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. ASP-DAC Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2011	J	`jnl`	Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. IEICE Trans. Electron. Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
2011	J	`jnl`	Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. IEEE Trans. Circuits Syst. Video Technol. Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
2011	J	`jnl`	Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2010	J	`jnl`	A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. IEICE Trans. Inf. Syst. Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
2010	J	`jnl`	An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. IEICE Trans. Electron. Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
2010	—	`conf`	An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. ERSA Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama
2010	—	`conf`	Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. ERSA Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2010	—	`conf`	Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. ERSA Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
2010	J	`jnl`	Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
2009	—	`conf`	A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. ERSA Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
2009	—	`conf`	A low-power FPGA based on autonomous fine-grain power-gating. ASP-DAC Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2009	—	`conf`	Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. ERSA Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2009	—	`conf`	An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. ERSA Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
2009	—	`conf`	FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. ERSA Masanori Hariyama, Keita Tanji, Michitaka Kameyama
2009	J	`jnl`	Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. IEICE Trans. Electron. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2009	J	`jnl`	Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. IEEE Trans. Very Large Scale Integr. Syst. Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama
2008	J	`jnl`	Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. IEICE Trans. Electron. Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama
2008	J	`jnl`	Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2008	J	`jnl`	Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. IEICE Trans. Electron. Masanori Hariyama, Shota Ishihara, Michitaka Kameyama
2008	A	`conf`	FPGA implementation of a vehicle detection algorithm using three-dimensional information. IPDPS Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama
2008	—	`conf`	Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. ERSA Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2008	J	`jnl`	Memory Allocation for Multi-Resolution Image Processing. IEICE Trans. Inf. Syst. Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama
2008	J	`jnl`	Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. IEICE Trans. Electron. Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
2008	—	`conf`	Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ERSA Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama
2006	J	`jnl`	A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates. IEICE Trans. Electron. Masanori Hariyama, Sho Ogata, Michitaka Kameyama
2006	—	`conf`	A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. APCCAS Masanori Hariyama, Michitaka Kameyama
2006	A	`conf`	Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. IPDPS Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
2006	—	`conf`	GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. APCCAS W. H. Muthumala, Masanori Hariyama, Michitaka Kameyama
2006	J	`jnl`	Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification. IEICE Trans. Electron. Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama
2006	—	`conf`	Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. ISVLSI Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi
2006	—	`conf`	Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ISMVL Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
2005	A	`conf`	Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. IPDPS Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama
2005	J	`jnl`	Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. IEICE Trans. Inf. Syst. Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama
2005	J	`jnl`	Editorial: VLSI Computing for Real-World Intelligent Systems. J. Robotics Mechatronics Masanori Hariyama
2005	J	`jnl`	FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama
2005	J	`jnl`	Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. IEEE Trans. Computers Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama
2005	J	`jnl`	Low-Power Field-Programmable VLSI Using Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
2005	—	`conf`	Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. ISVLSI Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
2004	—	`conf`	Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. ISVLSI Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
2004	—	`conf`	Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. ISVLSI Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama
2002	—	`conf`	High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. ISVLSI Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama
2001	A*	`conf`	VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. ICRA Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama
2000	J	`jnl`	Architecture of a high-performance stereo vision VLSI processor. Adv. Robotics Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama
2000	J	`jnl`	Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction. J. Robotics Mechatronics Hideki Kazama, Masanori Hariyama, Michitaka Kameyama
2000	J	`jnl`	Path Planning Based on Distance Transformation and Its VLSI Implementation. J. Robotics Mechatronics Masanori Hariyama, Michitaka Kameyama
2000	J	`jnl`	Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture. J. Robotics Mechatronics Masanori Hariyama, Michitaka Kameyama
1998	A*	`conf`	Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. ICRA Masanori Hariyama, Michitaka Kameyama
1997	J	`jnl`	A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. Syst. Comput. Jpn. Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama
1996	J	`jnl`	Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects. J. Robotics Mechatronics Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama
1994	J	`jnl`	Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles. J. Robotics Mechatronics Masanori Hariyama, Michitaka Kameyama