Masanori Furuta

38 papers C 8Journal 17Unranked 13

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Neuromorphic model of hippocampus place cells using an oscillatory interference technique for hardware implementation. Neuromorph. Comput. Eng. Zhaoqi Chen, Alia Nasrallah, Milad Alemohammad, Masanori Furuta, Ralph Etienne-Cummings
2021	—	`conf`	An Efficient Implementation of FPGA-based Object Detection Using Multi-scale Attention. MWSCAS Masanori Furuta, Koichiro Ban, Daisuke Kobayashi, Tomoyuki Shibata
2020	C	`conf`	Velocity-Tuned Oscillators for NeuroSLAM and Spatial Navigation. ISCAS Alia Nasrallah, Zhaoqi Chen, Milad Alemohammad, Adyant Balaji, Adam B. Cellon, Masanori Furuta, Ralph Etienne-Cummings
2019	J	`jnl`	Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. IEEE Trans. Very Large Scale Integr. Syst. Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura
2019	C	`conf`	Velocity-Controlled Oscillators for Hippocampal Navigation on Spiking Neuromorphic Hardware. ISCAS Adam B. Cellon, Adebayo A. Eisape, Masanori Furuta, Ralph Etienne-Cummings
2017	—	`conf`	28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. ISSCC Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura
2016	—	`conf`	19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. ISSCC Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura
2016	—	`conf`	26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. ISSCC Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
2016	—	`conf`	6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA. ISSCC Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura
2016	J	`jnl`	A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. IEEE J. Solid State Circuits Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
2016	J	`jnl`	A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Junya Matsuno, Masanori Furuta, Tetsuro Itakura, Tatsuji Matsuura, Akira Hyogo
2016	C	`conf`	A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB. ISCAS Junya Matsuno, Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii, Masanori Furuta, Tetsuro Itakura
2015	J	`jnl`	A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Furuta, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Junya Matsuno, Shigehito Saigusa, Tetsuro Itakura
2015	C	`conf`	A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors. ISCAS Yasuhiro Shinozuka, Kei Shiraishi, Masanori Furuta, Tetsuro Itakura
2014	—	`conf`	20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. ISSCC Shigehito Saigusa, Toshiya Mitomo, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Shusuke Kawai, Tong Wang, Masanori Furuta, Kei Shiraishi, Koichiro Ban, Seiichiro Horikawa, Tomoya Tandai, Ryoko Matsuo, Takeshi Tomizawa, Hiroaki Hoshino, Junya Matsuno, Yukako Tsutsumi, Ryoichi Tachibana, Osamu Watanabe, Tetsuro Itakura
2014	C	`conf`	A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC. ISCAS Kei Shiraishi, Daisuke Kurose, Masanori Furuta, Tetsuro Itakura
2013	—	`conf`	A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier. VLSI-DAT Junya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura
2013	J	`jnl`	A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Furuta, Ippei Akita, Junya Matsuno, Tetsuro Itakura
2013	J	`jnl`	All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal. IEEE Trans. Circuits Syst. I Regul. Pap. Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura
2012	C	`conf`	All-digital background calibration for time-interleaved ADC using pseudo aliasing signal. ISCAS Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura
2011	J	`jnl`	A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique. IEEE J. Solid State Circuits Masanori Furuta, Mai Nozawa, Tetsuro Itakura
2011	—	`conf`	A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier. A-SSCC Ippei Akita, Masanori Furuta, Junya Matsuno, Tetsuro Itakura
2010	—	`conf`	A 0.06mm ISSCC Masanori Furuta, Mai Nozawa, Tetsuro Itakura
2008	C	`conf`	An area-efficient sampling rate converter using negative feedback technique. ISCAS Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura
2007	J	`jnl`	A Digital-Calibration Technique for Redundant Radix-4 Pipelined Analog-to-Digital Converters. IEEE Trans. Instrum. Meas. Masanori Furuta, Shoji Kawahito, Daisuke Miyazaki
2007	—	`conf`	A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits. CICC Yukinari Nishikawa, Shoji Kawahito, Masanori Furuta, Toshihiro Tamura
2007	J	`jnl`	A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters. IEEE J. Solid State Circuits Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji Kawahito
2007	J	`jnl`	A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques. IEEE J. Solid State Circuits Kazutaka Honda, Masanori Furuta, Shoji Kawahito
2007	J	`jnl`	A Wide Dynamic Range CMOS Image Sensor with Improved 12-bit Column Parallel Cyclic ADCs. Inf. Media Technol. Jong-Ho Park, Shoji Kawahito, Masanori Furuta, Masaaki Sasaki, Yasuo Wakamori, Mitsuhito Mase, Yukihiro Ohta
2007	J	`jnl`	Design of Parallel Image Compression Circuits for High-speed CMOS Image Sensors. Inf. Media Technol. Yukinari Nishikawa, Shoji Kawahito, Masanori Furuta, Toshihiro Tamura
2006	C	`conf`	A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues. ISCAS Kazutaka Honda, Masanori Furuta, Shoji Kawahito
2006	J	`jnl`	Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits. IEICE Trans. Electron. Zheng Liu, Masanori Furuta, Shoji Kawahito
2005	—	`conf`	A cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors. ESSCIRC Masanori Furuta, Shoji Kawahito, Toru Inoue, Yukinari Nishikawa
2005	J	`jnl`	A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters. IEEE J. Solid State Circuits Mitsuhito Mase, Shoji Kawahito, Masaaki Sasaki, Yasuo Wakamori, Masanori Furuta
2005	J	`jnl`	Low-Power Design of High-Speed A/D Converters. IEICE Trans. Electron. Shoji Kawahito, Kazutaka Honda, Masanori Furuta, Nobuhiro Kawai, Daisuke Miyazaki
2003	J	`jnl`	A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture. IEEE J. Solid State Circuits Daisuke Miyazaki, Shoji Kawahito, Masanori Furuta
2003	—	`conf`	A 75mW 10bit 120MSample/s parallel pipeline ADC. ESSCIRC Daisuke Miyazaki, Masanori Furuta, Shoji Kawahito
2003	—	`conf`	A digitally skew correctable multi-phase clock generator using a master-slave DLL. ISCAS (1) Atsushi Suzuki, Shoji Kawahito, Daisuke Miyazaki, Masanori Furuta