Masanao Yamaoka

42 papers C 2Journal 16Unranked 24

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Annealing Machine-assisted Learning of Graph Neural Network for Combinatorial Optimization. CoRR Pablo Loyola, Kento Hasegawa, Andres Hoyos-Idobro, Kazuo Ono, Toyotaro Suzumura, Yu Hirate, Masanao Yamaoka
2021	—	`conf`	4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems. ISSCC Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, Masanao Yamaoka
2021	—	`conf`	A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems. A-SSCC Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao Yamaoka
2021	J	`jnl`	Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. Soft Comput. Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki
2021	J	`jnl`	STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
2020	—	`conf`	7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. ISSCC Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
2020	J	`jnl`	A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. IEEE J. Solid State Circuits Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka
2020	—	`conf`	CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem. ASP-DAC Chihiro Yoshimura, Masato Hayashi, Takashi Takemoto, Masanao Yamaoka
2020	J	`jnl`	Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. CoRR Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki
2019	—	`conf`	A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. ISSCC Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka
2019	—	`conf`	A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems. VLSI Circuits Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka
2019	J	`jnl`	A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines. IEICE Trans. Inf. Syst. Daisuke Oku, Kotaro Terada, Masato Hayashi, Masanao Yamaoka, Shu Tanaka, Nozomu Togawa
2019	—	`conf`	CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems. CICC Masanao Yamaoka, Takuya Okuyama, Masato Hayashi, Chihiro Yoshimura, Takashi Takemoto
2019	C	`conf`	Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	An Ising model mapping to solve rectangle packing problem. VLSI-DAT Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search. ReConFig Takashi Takemoto, Normann Mertig, Masato Hayashi, Saki Susa-Tanaka, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Tamiki Komatsuzaki, Masanao Yamaoka
2018	—	`conf`	Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity. TPNC Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki
2017	—	`conf`	An Ising Computer Based on Simulated Quantum Annealing by Path Integral Monte Carlo Method. ICRC Takuya Okuyama, Masato Hayashi, Masanao Yamaoka
2017	J	`jnl`	Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing. Int. J. Netw. Comput. Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Masanao Yamaoka
2016	J	`jnl`	A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing. IEEE J. Solid State Circuits Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2016	J	`jnl`	Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution. Int. J. Netw. Comput. Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2016	—	`conf`	Computing architecture to perform approximated simulated annealing for Ising models. ICRC Takuya Okuyama, Chihiro Yoshimura, Masato Hayashi, Masanao Yamaoka
2016	—	`conf`	FPGA-based Annealing Processor for Ising Model. CANDAR Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Masanao Yamaoka
2015	—	`conf`	24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing. ISSCC Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2015	—	`conf`	An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution. CANDAR Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2015	—	`conf`	Technology/circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution? VLSIC N. Sugii, G. Jurczak, Masanao Yamaoka, A. Molnar, J. Tham, T. Piliszczuk, O. Nalamasu, J. Hausner, Shu Tanaka, Tadaaki Yamauchi, S. Sivaram, C. Diaz, W. Dai
2014	C	`conf`	An energy-efficient parallel-processing method based on master-hibernating DVFS. ISCAS Masaki Hamamoto, Masanao Yamaoka
2013	—	`conf`	Spatial computing architecture using randomness of memory cell stability under voltage control. ECCTD Chihiro Yoshimura, Masanao Yamaoka, Hidetaka Aoki, Hiroyuki Mizuno
2010	J	`jnl`	Adaptive Circuits for the 0.5-V Nanoscale CMOS Era. IEICE Trans. Electron. Kiyoo Itoh, Masanao Yamaoka, Takashi Oshima
2009	—	`conf`	A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. CICC Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada
2008	—	`conf`	65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. ISSCC Masanao Yamaoka, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada
2008	—	`conf`	A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. ESSCIRC Masanao Yamaoka, Kenichi Osada, Takayuki Kawahara
2007	—	`conf`	Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ACM Great Lakes Symposium on VLSI Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara
2007	—	`conf`	Low-voltage limitations of memory-rich nano-scale CMOS LSIs. ESSCIRC Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka
2007	—	`conf`	Operating-margin-improved SRAM with column-at-a-time body-bias control technique. ESSCIRC Masanao Yamaoka, Takayuki Kawahara
2006	J	`jnl`	90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. IEEE J. Solid State Circuits Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara
2006	—	`conf`	A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design. SoCC Masanao Yamaoka, Hidetoshi Onodera
2006	J	`jnl`	SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors. IEEE J. Solid State Circuits Masanao Yamaoka, Ryuta Tsuchiya, Takayuki Kawahara
2005	J	`jnl`	A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. IEEE J. Solid State Circuits Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada
2005	J	`jnl`	A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. IEICE Trans. Electron. Makoto Ishikawa, Tatsuya Kamei, Yuki Kondo, Masanao Yamaoka, Yasuhisa Shimazaki, Motokazu Ozawa, Saneaki Tamaki, Mikio Furuyama, Tadashi Hoshi, Fumio Arakawa, Osamu Nishii, Kenji Hirose, Shinichi Yoshioka, Toshihiro Hattori
2004	J	`jnl`	0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. IEEE J. Solid State Circuits Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi
2002	J	`jnl`	A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit. IEEE J. Solid State Circuits Masanao Yamaoka, Kazumasa Yanagisawa, Shoji Shukuri, Katsuhiro Norisue, Koichiro Ishibashi