Masami Nakajima

17 papers Journal 8Unranked 9
YearRankTypeTitle / Venue / Authors
2016 — conf
A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes.
COOL Chips
Masami Nakajima, Ichiro Naka, Fumihiro Matsushima, Tadaaki Yamauchi
2011 J jnl
A Scalable Massively Parallel Processor for Real-Time Image Processing.
IEEE J. Solid State Circuits
Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
2011 — conf
Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G.
CVPR Workshops
Yushi Moko, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa, Masami Nakajima, Kazutami Arimoto
2010 — conf
A scalable massively parallel processor for real-time image processing.
ISSCC
Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
2009 J jnl
Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications.
IEEE J. Solid State Circuits
Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu
2008 J jnl
Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors.
IEEE J. Solid State Circuits
Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto
2008 — conf
Heterogeneous multicore SoC for secure multimedia applications.
CICC
Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu
2007 — conf
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.
ISMVL
Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto
2007 J jnl
The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture.
IEEE J. Solid State Circuits
Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto
2007 J jnl
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.
IEEE J. Solid State Circuits
Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu
2006 — conf
A 40GOPS 250mW massively parallel processor based on matrix architecture.
ISSCC
Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu
2006 J jnl
Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture.
IEICE Trans. Electron.
Toru Shimizu, Masami Nakajima, Masahiro Kainaga
2005 J jnl
Implementation of Face Recognition Processing Using an Embedded Processor.
J. Robotics Mechatronics
Hiroyuki Kondo, Masami Nakajima, Miroslaw Bober, Krzysztof Kucharski, Osamu Yamamoto, Toru Shimizu
2004 J jnl
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory.
IEEE J. Solid State Circuits
Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu
1996 — conf
Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy.
ISMVL
Masami Nakajima, Michitaka Kameyama
1994 — conf
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel
ISMVL
Masami Nakajima, Michitaka Kameyama
1993 — conf
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations.
ISMVL
Masami Nakajima, Michitaka Kameyama