Masaki Tsukude

13 papers A 2Journal 11

Year	Rank	Type	Title / Venue / Authors
1998	J	`jnl`	400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada
1997	J	`jnl`	A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. IEEE J. Solid State Circuits Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto
1997	J	`jnl`	High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. IEEE J. Solid State Circuits Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada
1996	J	`jnl`	A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. IEEE J. Solid State Circuits Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe
1996	J	`jnl`	SOI-DRAM circuit technologies for low power high speed multigiga scale memories. IEEE J. Solid State Circuits Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto
1995	J	`jnl`	Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs. IEEE J. Solid State Circuits Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto
1994	J	`jnl`	An experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE J. Solid State Circuits Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara
1993	J	`jnl`	Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Des. Test Comput. Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima
1992	J	`jnl`	A 34-ns 16-Mb DRAM with controllable voltage down-converter. IEEE J. Solid State Circuits Hideto Hidaka, Kazutami Arimoto, Kazutoshi Hirayama, Masanori Hayashikoshi, Mikio Asakura, Masaki Tsukude, Tsukasa Oishi, Shinji Kawai, Katsuhiro Suma, Yasuhiro Konishi, Koji Tanaka, Wataru Wakamiya, Yoshikazu Ohno, Kazuyasu Fujishima
1992	A	`conf`	A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima
1990	J	`jnl`	A speed-enhanced DRAM array architecture with embedded ECC. IEEE J. Solid State Circuits Kazutami Arimoto, Yoshio Matsuda, Kiyohiro Furutani, Masaki Tsukude, Tsukasa Ooishi, Koichiro Mashiko, Kuzuyasu Fujishima
1989	J	`jnl`	A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. IEEE J. Solid State Circuits Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano
1989	A	`conf`	A New Array Architecture for Parallel Testing in VLSI Memories. ITC Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima