Masakazu Yamashina

23 papers Misc 2Journal 18Unranked 3

Year	Rank	Type	Title / Venue / Authors
2002	—	`conf`	A low-power W-CDMA demodulator using specially-designed micro-DSPs. CICC Hiroyuki Igura, Masaru Hirata, Junya Yamada, Masakazu Yamashina, Shigeru Ono
2002	J	`jnl`	Guest editorial. IEEE J. Solid State Circuits Masakazu Yamashina, Shekhar Y. Borkar
2001	J	`jnl`	Guest editorial. IEEE J. Solid State Circuits David B. Scott, Masakazu Yamashina
2000	J	`jnl`	A Single-Chip Multiprocessor for Smart Terminals. IEEE Micro Masato Edahiro, Satoshi Matsushita, Masakazu Yamashina, Naoki Nishi
2000	—	`conf`	Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk. ASP-DAC Masakazu Yamashina, Masato Motomura
2000	—	`conf`	Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI. CICC Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina
1999	J	`jnl`	A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. IEEE J. Solid State Circuits Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina
1998	J	`jnl`	An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing. IEEE J. Solid State Circuits Hiroyuki Igura, Yukihiro Naito, Kenya Kazama, Ichiro Kuroda, Masato Motomura, Masakazu Yamashina
1998	Misc	`conf`	An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration. FCCM Masato Motomura, Yoshiharu Aimoto, Atsufkni Shibayama, Yoshikazu Yabe, Masakazu Yamashina
1997	J	`jnl`	A 0.25-μm CMOS 0.9-V 100-MHz DSP core. IEEE J. Solid State Circuits Masanori Izumikawa, Hiroyuki Igura, Hitoshi Wakabayashi, Ken Nakajima, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina
1997	J	`jnl`	A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. IEEE J. Solid State Circuits Masayuki Mizuno, Yasushi Ooi, Naoya Hayashi, Junichi Goto, Masatoshi Hozumi, Koichiro Furuta, Atsufumi Shibayama, Yoetsu Nakazawa, Osamu Ohnishi, Shu-Yu Zhu, Yutaka Yokoyama, Yoichi Katayama, Hideto Takano, Noriyuki Miki, Yuzo Senda, Ichiro Tamitani, Masakazu Yamashina
1997	Misc	`conf`	An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU. ICASSP Yasushi Ooi, Osamu Ohnishi, Yutaka Yokoyama, Yoichi Katayama, Masayuki Mizuno, Masakazu Yamashina, Hideo Takano, Naoya Hayashi, Ichiro Tamitani
1996	J	`jnl`	A GHz MOS adaptive pipeline technique using MOS current-mode logic. IEEE J. Solid State Circuits Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada
1996	J	`jnl`	A current direction sense technique for multiport SRAM's. IEEE J. Solid State Circuits Masanori Izumikawa, Masakazu Yamashina
1996	J	`jnl`	Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. IEEE J. Solid State Circuits Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina
1995	J	`jnl`	Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. IEEE J. Solid State Circuits Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina
1994	J	`jnl`	A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. IEEE J. Solid State Circuits Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina
1994	J	`jnl`	A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. IEEE J. Solid State Circuits Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada
1994	J	`jnl`	A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor. IEEE J. Solid State Circuits Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada
1993	J	`jnl`	A 300-MHz 16-b BiCMOS video signal processor. IEEE J. Solid State Circuits Toshiaki Inoue, Junichi Goto, Masakazu Yamashina, Kazumasa Suzuki, Masahiro Nomura, Youichi Koseki, Tohru Kimura, Takao Atsumo, Masato Motomura, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada, Masahide Takada
1991	J	`jnl`	250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI. IEEE J. Solid State Circuits Junichi Goto, Koichi Ando, Toshiaki Inoue, Masakazu Yamashina, Hachiro Yamada, Tadayoshi Enomoto
1989	J	`jnl`	A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI. IEEE J. Solid State Circuits Masakazu Yamashina, Junichi Goto, Fuyuki Okamoto, Koichi Ando, Hachiro Yamada, Tadahiko Horiuchi, Kimiko Nakamura, Tadayoshi Enomoto
1988	J	`jnl`	A microprogrammable real-time video signal processor (VSP) for motion compensation. IEEE J. Solid State Circuits Masakazu Yamashina, Tadayoshi Enomoto, Takemitsu Kunio, Ichiro Tamitani, Hidenobu Harasaki, Yukio Endo, Takao Nishitani, Masao Satoh, Koichi Kikuchi