Masakazu Aoki

24 papers Journal 22Unranked 2
YearRankTypeTitle / Venue / Authors
2008 J jnl
Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis.
IEICE Trans. Electron.
Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda
2005 — conf
Approach for physical design in sub-100 nm era.
ISCAS (6)
Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki
2005 — conf
Challenge: variability characterization and modeling for 65- to 90-nm processes.
CICC
Hiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki
2005 J jnl
Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip.
IEICE Trans. Electron.
Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda
1999 J jnl
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.
IEEE J. Solid State Circuits
Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura
1998 J jnl
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register.
IEEE J. Solid State Circuits
Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana
1995 J jnl
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.
IEEE J. Solid State Circuits
Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda
1995 J jnl
Low-noise, high-speed data transmission using a ringing-canceling output buffer.
IEEE J. Solid State Circuits
Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki
1994 J jnl
A charge recycle refresh for Gb-scale DRAM's in file applications.
IEEE J. Solid State Circuits
Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki
1994 J jnl
Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs.
IEEE J. Solid State Circuits
Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa
1994 J jnl
Subthreshold-current reduction circuits for multi-gigabit DRAM's.
IEEE J. Solid State Circuits
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
1994 J jnl
Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's.
IEEE J. Solid State Circuits
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
1993 J jnl
256-Mb DRAM circuit technologies for file applications.
IEEE J. Solid State Circuits
Goro Kitsukawa, Masashi Horiguchi, Yoshiki Kawajiri, Takayuki Kawahara, Takesada Akiba, Yasushi Kawase, Toshikazu Tachibana, Takeshi Sakai, Masakazu Aoki, Syoji Shukuri, Kazuhiko Sagara, Ryo Nagai, Yuzuru Ohji, Nono Hasegawa, Natsuki Yokoyama, Teruaki Kisu, Hisaomi Yamashita, Tokuo Kure, Takashi Nishida
1993 J jnl
A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays.
IEEE J. Solid State Circuits
Takayuki Kawahara, Takeshi Sakata, Kiyoo Itoh, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, Masakazu Aoki
1993 J jnl
A single 1.5-V digital chip for a 10
IEEE Trans. Neural Networks
Takao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito
1993 J jnl
Sub-1-V swing internal bus architecture for future low-power ULSIs.
IEEE J. Solid State Circuits
Yoshinobu Nakagome, Kiyoo Itoh, Masanori Isoda, Kan Takeuchi, Masakazu Aoki
1993 J jnl
Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs).
IEEE J. Solid State Circuits
Takayuki Kawahara, Masashi Horiguchi, Yoshiki Kawajiri, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki
1991 J jnl
A flexible redundancy technique for high-density DRAMs.
IEEE J. Solid State Circuits
Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh, Tetsuro Matsumoto
1991 J jnl
Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM.
IEEE J. Solid State Circuits
Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki
1991 J jnl
Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test.
IEEE J. Solid State Circuits
Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Gyoo Itoh, Kazuhiko Kajigaya, Atsushi Nozoe, Tetsuro Matsumoto
1990 J jnl
A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier.
IEEE J. Solid State Circuits
Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto
1989 J jnl
A 1.5-V DRAM for battery-based applications.
IEEE J. Solid State Circuits
Masakazu Aoki, Jun Etoh, Kiyoo Itoh, Shin Kimura, Yoshifumi Kawamoto
1989 J jnl
New DRAM noise generation under half-V
IEEE J. Solid State Circuits
Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh
1988 J jnl
An experimental large-capacity semiconductor file memory using 16-levels/cell storage.
IEEE J. Solid State Circuits
Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi