Masahiro Sowa

41 papers C 6Misc 3Journal 23Unranked 9
YearRankTypeTitle / Venue / Authors
2012 J jnl
An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Duc-Hung Le, Katsumi Inoue, Masahiro Sowa, Cong-Kha Pham
2010 J jnl
Compiling for Reduced Bit-Width Queue Processors.
J. Signal Process. Syst.
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2009 J jnl
Compiler Support for Code Size Reduction Using a Queue-Based Processor.
Trans. High Perform. Embed. Archit. Compil.
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2009 J jnl
Design and implementation of a queue compiler.
Microprocess. Microsystems
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2009 J jnl
Efficient compilation for queue size constrained queue processors.
Parallel Comput.
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2008 J jnl
A new code generation algorithm for 2-offset producer order queue computation model.
Comput. Lang. Syst. Struct.
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2008 J jnl
Dual-execution mode processor architecture.
J. Supercomput.
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
2008 — conf
Quantitative Evaluation of Common Subexpression Elimination on Queue Machines.
ISPAN
Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek
2008 J jnl
The QC-2 parallel Queue processor architecture.
J. Parallel Distributed Comput.
Ben A. Abderazek, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa
2007 C conf
An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model.
EUC
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2007 J jnl
Dual-Execution Mode Processor Architecture For Embedded Applications.
J. Mobile Multimedia
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
2007 — conf
Mathematical Model for Multiobjective Synthesis of NoC Architectures.
ICPP Workshops
Ben A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa
2007 C conf
New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP.
PDCAT
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2007 J jnl
Optimizing Reaching Definitions Overhead in Queue Processors.
J. Convergence Inf. Technol.
Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2007 C conf
Queue Register File Optimization Algorithm for QueueCore Processor.
SBAC-PAD
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2006 J jnl
Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters.
Inf. Media Technol.
Ta Quoc Viet, Tsutomu Yoshinaga, Ben A. Abderazek, Masahiro Sowa
2006 J jnl
Design and architecture for an embedded 32-bit QueueCore.
J. Embed. Comput.
Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa
2006 J jnl
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.
J. Supercomput.
Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
2006 — conf
On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation.
ISPA Workshops
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
2006 — conf
Scalable Core-Based Methodology and Synthesizable Core for Systematic Design.
ICPP Workshops
Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
2005 C conf
An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture.
EUC
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa
2005 C conf
Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.
EUC
Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa
2005 J jnl
Parallel Queue Processor Architecture Based on Produced Order Computation Model.
J. Supercomput.
Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga
2003 C conf
On the Design of a Register Queue Based Processor Architecture (FaRM-rq).
ISPA
Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa
2002 — conf
Compiler-Controlled Parallelism-Independent Scheduling Method for Cluster Computing Systems.
HPCS
Kirilka Nikolova, Masahiro Sowa
2002 — conf
Compiler-Controlled Parallelism-Independent Scheduling for Parallel and Distributed Systems.
PARA
Kirilka Nikolova, Sou Pei You, Masahiro Sowa
2002 — conf
Proposal and Design of a Parallel Queue Processor Architecture (PQP).
IASTED PDCS
Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga
2001 J jnl
Access route control by an extended key/lock scheme.
Comput. Syst. Sci. Eng.
Soichi Shigeta, Kentaro Shimizu, Masahiro Sowa
1997 Misc conf
Intruction Fetch Mechanism for PN-Superscalar.
PDPTA
Shusuke Okamoto, Masahiro Sowa
1997 Misc conf
Program Controlled Cache Memory on Parallel Computer.
PDPTA
Mitsuaki Nakasumi, Shusuke Okamoto, Masahiro Sowa
1996 Misc conf
Hybrid Processor Based on VLIW and PN-Superscalar.
PDPTA
Shusuke Okamoto, Masahiro Sowa
1994 — conf
V++: An Instruction-Restructurable Processor Architecture.
HICSS (1)
Takaya Arita, Hiromitsu Takagi, Masahiro Sowa
1993 J jnl
A static processor-scheduling algorithm resistive to dynamic fluctuation of execution timing.
Syst. Comput. Jpn.
Hiromitsu Takagi, Takaya Arita, Masahiro Sowa
1992 J jnl
Delayed instruction execution on a long instruction word (LIW) computer.
Syst. Comput. Jpn.
Komei Kato, Takaya Arita, Masahiro Sowa
1992 J jnl
Performance of the PN superscalar processor as estimated by simulation.
Syst. Comput. Jpn.
Takaya Arita, Hiroaki Ito, Masahiro Sowa
1991 J jnl
High Speed Synchronization for a Statically Scheduled Superscalar Processor.
Int. J. High Speed Comput.
Takaya Arita, Masahiro Sowa
1991 J jnl
Parallel execution on the function-partitioned processor with multiple instruction streams.
Syst. Comput. Jpn.
Masahiro Sowa, Takaya Arita, Tadaaki Kawamura, Hiromitsu Takagi
1987 J jnl
A Method for Speeding up Serial Processing in Dataflow Computers by Means of a Program Counter.
Comput. J.
Masahiro Sowa
1987 J jnl
Performance of a simulated dataflow computer DFNDR-2.
Syst. Comput. Jpn.
Masahiro Sowa, Akitoshi Kamimura
1985 — conf
A Timed Petri Net Model and Simulation of a Dataflow Computer.
PNPM
T. Smigelski, Tadao Murata, Masahiro Sowa
1982 J jnl
A Data Flow Computer Architecture with Program and Token Memories.
IEEE Trans. Computers
Masahiro Sowa, Tadao Murata