Masahiro Sakamoto

14 papers C 1Journal 6Unranked 7
YearRankTypeTitle / Venue / Authors
2024 — conf
Development and Implementation Results of a DX Literacy Standard Skills Survey Using Generative AI.
IIAI-AAI
Masahiro Sakamoto, Yukihiro Matsubara, Kousuke Mouri
2024 J jnl
Page Turning Using Assistive Robot with Low-Degree-of-Freedom Hand.
Sensors
Hidetoshi Ikeda, Yuta Mizukami, Masahiro Sakamoto, Takumi Saeki, Hokyoo Lee, Masakazu Hori
2023 C conf
Learning Analysis infrastructure to support optimal learning based on IRT and Video Enrollment Data.
ICCE
Masahiro Sakamoto, Yukihiro Matsubara, Kousuke Mouri
2015 J jnl
A Sigma-Delta Domain Lowpass Wave Filter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hisato Fujisaka, Takeshi Kamio, Chang-Jun Ahn, Masahiro Sakamoto, Kazuhisa Haeiwa
2014 — conf
Development of immersive display system of web service in living space.
GCCE
Hiroshi Sugimura, Kazuki Utsumi, Masayuki Kaneko, Kazuki Arima, Masahiro Sakamoto, Yuki Imaizumi, Tomoki Watanabe, Masao Isshiki
2012 J jnl
Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing - Part I: Addition, Approximate Transcendental Functions, and Log-Domain Operations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hisato Fujisaka, Takeshi Kamio, Chang-Jun Ahn, Masahiro Sakamoto, Kazuhisa Haeiwa
2012 J jnl
Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing - Part II: Multiplication and Algebraic Functions.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hisato Fujisaka, Masahiro Sakamoto, Chang-Jun Ahn, Takeshi Kamio, Kazuhisa Haeiwa
2004 — conf
A binary-quantized pseudo-diffusion system.
ISCAS (4)
Hisato Fujisaka, Daisuke Hamano, Masahiro Sakamoto, Takeshi Kamio
2004 — conf
A design of 4-operand redundant binary parallel adder using neuron MOS.
ISCAS (2)
Masahiro Sakamoto, Shuusaku Mizukami, Daisuke Hamano, Hisato Fujisaka
2002 J jnl
Bit-Stream Signal Processing Circuits and Their Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hisato Fujisaka, Masahiro Sakamoto, Mititada Morisue
2002 J jnl
Design of a multiple-operand redundant binary adder.
Syst. Comput. Jpn.
Masahiro Sakamoto, Daisuke Hamano, Mititada Morisue
2002 — conf
Piecewise linear operations on sigma-delta modulated signals.
ICECS
Yuji Hidaka, Hisato Fujisaka, Masahiro Sakamoto, Mititada Morisue
1999 — conf
Arithmetic circuits for single-bit digital signal processing.
ICECS
Hisato Fujisaka, Naoyuki Masuda, Masahiro Sakamoto, Mititada Morisue
1998 — conf
A Josephson Ternary Memory Circuit.
ISMVL
Mititada Morisue, Jun Endo, Toshimitu Morooka, Nobuhiro Shimizu, Masahiro Sakamoto