Masahiro Nomura

87 papers A* 7A 12B 6Journal 48Unranked 14

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Beyond Match Maximization and Fairness: Retention-Optimized Two-Sided Matching. CoRR Ren Kishimoto, Rikiya Takehi, Koichi Tanaka, Masahiro Nomura, Riku Togashi, Yoji Tomita, Yuta Saito
2026	J	`jnl`	Takeuchi's Information Criteria as Generalization Measures for DNNs Close to NTK Regime. CoRR Hiroki Naganuma, Taiji Suzuki, Rio Yokota, Masahiro Nomura, Kohta Ishikawa, Ikuro Sato
2025	B	`conf`	A Memetic Algorithm based on Variational Autoencoder for Black-Box Discrete Optimization with Epistasis among Parameters. CEC Aoi Kato, Kenta Kojima, Masahiro Nomura, Isao Ono
2025	J	`jnl`	A Memetic Algorithm based on Variational Autoencoder for Black-Box Discrete Optimization with Epistasis among Parameters. CoRR Aoi Kato, Kenta Kojima, Masahiro Nomura, Isao Ono
2025	J	`jnl`	CMA-ES with Learning Rate Adaptation. ACM Trans. Evol. Learn. Optim. Masahiro Nomura, Youhei Akimoto, Isao Ono
2025	A	`conf`	CatCMA with Margin: Stochastic Optimization for Continuous, Integer, and Categorical Variables. GECCO Ryoki Hamano, Masahiro Nomura, Shota Saito, Kento Uchida, Shinichi Shirakawa
2025	J	`jnl`	CatCMA with Margin: Stochastic Optimization for Continuous, Integer, and Categorical Variables. CoRR Ryoki Hamano, Masahiro Nomura, Shota Saito, Kento Uchida, Shinichi Shirakawa
2025	A*	`conf`	Instance-wise Supervision-level Optimization in Active Learning. CVPR Shinnosuke Matsuo, Riku Togashi, Ryoma Bise, Seiichi Uchida, Masahiro Nomura
2025	J	`jnl`	Instance-wise Supervision-level Optimization in Active Learning. CoRR Shinnosuke Matsuo, Riku Togashi, Ryoma Bise, Seiichi Uchida, Masahiro Nomura
2025	B	`conf`	Multi-start Optimization Method via Scalarization based on Target Point-based Tchebycheff Distance for Multi-objective Optimization. CEC Kota Nagakane, Masahiro Nomura, Isao Ono
2025	J	`jnl`	Multi-start Optimization Method via Scalarization based on Target Point-based Tchebycheff Distance for Multi-objective Optimization. CoRR Kota Nagakane, Masahiro Nomura, Isao Ono
2024	—	`conf`	CMA-ES for Discrete and Mixed-Variable Optimization on Sets of Points. PPSN (2) Kento Uchida, Ryoki Hamano, Masahiro Nomura, Shota Saito, Shinichi Shirakawa
2024	J	`jnl`	CMA-ES for Discrete and Mixed-Variable Optimization on Sets of Points. CoRR Kento Uchida, Ryoki Hamano, Masahiro Nomura, Shota Saito, Shinichi Shirakawa
2024	A	`conf`	CMA-ES for Safe Optimization. GECCO Kento Uchida, Ryoki Hamano, Masahiro Nomura, Shota Saito, Shinichi Shirakawa
2024	J	`jnl`	CMA-ES for Safe Optimization. CoRR Kento Uchida, Ryoki Hamano, Masahiro Nomura, Shota Saito, Shinichi Shirakawa
2024	J	`jnl`	CMA-ES with Learning Rate Adaptation. CoRR Masahiro Nomura, Youhei Akimoto, Isao Ono
2024	A	`conf`	CatCMA : Stochastic Optimization for Mixed-Category Problems. GECCO Ryoki Hamano, Shota Saito, Masahiro Nomura, Kento Uchida, Shinichi Shirakawa
2024	J	`jnl`	CatCMA : Stochastic Optimization for Mixed-Category Problems. CoRR Ryoki Hamano, Shota Saito, Masahiro Nomura, Kento Uchida, Shinichi Shirakawa
2024	A	`conf`	Effective Off-Policy Evaluation and Learning in Contextual Combinatorial Bandits. RecSys Tatsuhiro Shimizu, Koichi Tanaka, Ren Kishimoto, Haruka Kiyohara, Masahiro Nomura, Yuta Saito
2024	J	`jnl`	Effective Off-Policy Evaluation and Learning in Contextual Combinatorial Bandits. CoRR Tatsuhiro Shimizu, Koichi Tanaka, Ren Kishimoto, Haruka Kiyohara, Masahiro Nomura, Yuta Saito
2024	J	`jnl`	Harnessing the Latent Diffusion Model for Training-Free Image Style Transfer. CoRR Kento Masui, Mayu Otani, Masahiro Nomura, Hideki Nakayama
2024	—	`conf`	Hot off the Press: Towards Practical Preferential Bayesian Optimization with Skew Gaussian Processes. GECCO Companion Shion Takeno, Masahiro Nomura, Masayuki Karasuyama
2024	A*	`conf`	Hyperparameter Optimization Can Even Be Harmful in Off-Policy Learning and How to Deal with It. IJCAI Yuta Saito, Masahiro Nomura
2024	J	`jnl`	Hyperparameter Optimization Can Even be Harmful in Off-Policy Learning and How to Deal with It. CoRR Yuta Saito, Masahiro Nomura
2024	J	`jnl`	Marginal Probability-Based Integer Handling for CMA-ES Tackling Single- and Multi-Objective Mixed-Integer Black-Box Optimization. ACM Trans. Evol. Learn. Optim. Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
2024	—	`conf`	Natural Gradient Interpretation of Rank-One Update in CMA-ES. PPSN (2) Ryoki Hamano, Shinichi Shirakawa, Masahiro Nomura
2024	J	`jnl`	Natural Gradient Interpretation of Rank-One Update in CMA-ES. CoRR Ryoki Hamano, Shinichi Shirakawa, Masahiro Nomura
2024	A*	`conf`	Off-Policy Evaluation of Slate Bandit Policies via Optimizing Abstraction. WWW Haruka Kiyohara, Masahiro Nomura, Yuta Saito
2024	J	`jnl`	Off-Policy Evaluation of Slate Bandit Policies via Optimizing Abstraction. CoRR Haruka Kiyohara, Masahiro Nomura, Yuta Saito
2024	J	`jnl`	cmaes : A Simple yet Practical Python Library for CMA-ES. CoRR Masahiro Nomura, Masashi Shibata
2023	A	`conf`	(1+1)-CMA-ES with Margin for Discrete and Mixed-Integer Problems. GECCO Yohei Watanabe, Kento Uchida, Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
2023	J	`jnl`	(1+1)-CMA-ES with Margin for Discrete and Mixed-Integer Problems. CoRR Yohei Watanabe, Kento Uchida, Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
2023	A	`conf`	CMA-ES with Learning Rate Adaptation: Can CMA-ES with Default Population Size Solve Multimodal and Noisy Problems? GECCO Masahiro Nomura, Youhei Akimoto, Isao Ono
2023	J	`jnl`	CMA-ES with Learning Rate Adaptation: Can CMA-ES with Default Population Size Solve Multimodal and Noisy Problems? CoRR Masahiro Nomura, Youhei Akimoto, Isao Ono
2023	A*	`conf`	Towards Practical Preferential Bayesian Optimization with Skew Gaussian Processes. ICML Shion Takeno, Masahiro Nomura, Masayuki Karasuyama
2023	J	`jnl`	Towards Practical Preferential Bayesian Optimization with Skew Gaussian Processes. CoRR Shion Takeno, Masahiro Nomura, Masayuki Karasuyama
2022	—	`conf`	Benchmarking CMA-ES with margin on the bbob-mixint testbed. GECCO Companion Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
2022	J	`jnl`	CMA-ES with Margin for Single-and Multi-Objective Mixed-Integer Black-Box Optimization. CoRR Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
2022	J	`jnl`	CMA-ES with Margin: Lower-Bounding Marginal Probability for Mixed-Integer Black-Box Optimization. CoRR Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
2022	A	`conf`	CMA-ES with margin: lower-bounding marginal probability for mixed-integer black-box optimization. GECCO Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
2022	B	`conf`	Fast Moving Natural Evolution Strategy for High-Dimensional Problems. CEC Masahiro Nomura, Isao Ono
2022	J	`jnl`	Fast Moving Natural Evolution Strategy for High-Dimensional Problems. CoRR Masahiro Nomura, Isao Ono
2022	J	`jnl`	Multiobjective Tree-Structured Parzen Estimator. J. Artif. Intell. Res. Yoshihiko Ozaki, Yuki Tanigaki, Shuhei Watanabe, Masahiro Nomura, Masaki Onishi
2022	J	`jnl`	Optimal Fixed-Budget Best Arm Identification using the Augmented Inverse Probability Weighting Estimator in Two-Armed Gaussian Bandits with Unknown Variances. CoRR Masahiro Kato, Kaito Ariu, Masaaki Imaizumi, Masatoshi Uehara, Masahiro Nomura, Chao Qin
2022	A*	`conf`	Towards Resolving Propensity Contradiction in Offline Recommender Learning. IJCAI Yuta Saito, Masahiro Nomura
2022	B	`conf`	Towards a Principled Learning Rate Adaptation for Natural Evolution Strategies. EvoApplications Masahiro Nomura, Isao Ono
2021	B	`conf`	Distance-weighted Exponential Natural Evolution Strategy for Implicitly Constrained Black-Box Function Optimization. CEC Masahiro Nomura, Nobuyuki Sakai, Nobusumi Fukushima, Isao Ono
2021	A	`conf`	Efficient Hyperparameter Optimization under Multi-Source Covariate Shift. CIKM Masahiro Nomura, Yuta Saito
2021	—	`conf`	Natural Evolution Strategy for Unconstrained and Implicitly Constrained Problems with Ridge Structure. SSCI Masahiro Nomura, Isao Ono
2021	J	`jnl`	Natural Evolution Strategy for Unconstrained and Implicitly Constrained Problems with Ridge Structure. CoRR Masahiro Nomura, Isao Ono
2021	J	`jnl`	Towards a Principled Learning Rate Adaptation for Natural Evolution Strategies. CoRR Masahiro Nomura, Isao Ono
2021	A*	`conf`	Warm Starting CMA-ES for Hyperparameter Optimization. AAAI Masahiro Nomura, Shuhei Watanabe, Youhei Akimoto, Yoshihiko Ozaki, Masaki Onishi
2020	B	`conf`	Evaluating Initialization of Nelder-Mead Method for Hyperparameter Optimization in Deep Learning. ICPR Shintaro Takenaga, Shuhei Watanabe, Masahiro Nomura, Yoshihiko Ozaki, Masaki Onishi, Hitoshi Habe
2020	J	`jnl`	Multi-Source Unsupervised Hyperparameter Optimization. CoRR Masahiro Nomura, Yuta Saito
2020	J	`jnl`	Simple and Scalable Parallelized Bayesian Optimization. CoRR Masahiro Nomura
2020	J	`jnl`	Warm Starting CMA-ES for Hyperparameter Optimization. CoRR Masahiro Nomura, Shuhei Watanabe, Youhei Akimoto, Yoshihiko Ozaki, Masaki Onishi
2019	J	`jnl`	A Simple Heuristic for Bayesian Optimization with A Low Budget. CoRR Masahiro Nomura, Kenshi Abe
2019	—	`conf`	Heat Transfer in Nanostructured Si and Heat Flux Control Technique. 3DIC Masahiro Nomura
2019	J	`jnl`	On Fail-Stop Signature Schemes with IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masahiro Nomura, Katsuhiro Nakamura
2014	J	`jnl`	Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. IEEE J. Solid State Circuits Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
2013	J	`jnl`	Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. IEEE J. Solid State Circuits Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2013	—	`conf`	Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits. ISSCC Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
2013	J	`jnl`	Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2013	—	`conf`	Variation-aware subthreshold logic circuit design. ASICON Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	—	`conf`	13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	—	`conf`	24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V ISQED Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai
2012	J	`jnl`	A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. IEEE J. Solid State Circuits Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno
2012	—	`conf`	Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. CICC Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	J	`jnl`	Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. IEEE Trans. Circuits Syst. II Express Briefs Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	—	`conf`	12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. ESSCIRC Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai
2011	A	`conf`	12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V ISLPED Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	A*	`conf`	A closed-form expression for estimating minimum operating voltage (V DAC Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	A	`conf`	Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. ISLPED Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
2011	J	`jnl`	Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. IEEE J. Solid State Circuits Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi
2011	J	`jnl`	Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. IEEE Trans. Circuits Syst. II Express Briefs Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	A	`conf`	Reduction of minimum operating voltage (V ISLPED Kentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
2010	A	`conf`	Misleading energy and performance claims in sub/near threshold digital systems. ICCAD Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai
2008	J	`jnl`	A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations. IEEE J. Solid State Circuits Yoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara
2006	J	`jnl`	A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. IEEE J. Solid State Circuits Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake
2006	J	`jnl`	An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques. IEICE Trans. Electron. Masahiro Nomura, Taku Ohsawa, Koichi Takeda, Yoetsu Nakazawa, Yoshinori Hirota, Yasuhiko Hagihara, Naoki Nishi
2006	J	`jnl`	Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. IEEE J. Solid State Circuits Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara
2006	—	`conf`	Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit. ISSCC Koichi Takeda, Hidetoshi Ikeda, Yasuhiko Hagihara, Masahiro Nomura, Hiroyuki Kobatake
1999	J	`jnl`	A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. IEEE J. Solid State Circuits Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina
1994	J	`jnl`	A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. IEEE J. Solid State Circuits Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada
1994	J	`jnl`	A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor. IEEE J. Solid State Circuits Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada
1993	J	`jnl`	A 300-MHz 16-b BiCMOS video signal processor. IEEE J. Solid State Circuits Toshiaki Inoue, Junichi Goto, Masakazu Yamashina, Kazumasa Suzuki, Masahiro Nomura, Youichi Koseki, Tohru Kimura, Takao Atsumo, Masato Motomura, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada, Masahide Takada
1990	—	`conf`	Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. ISMVL Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi