Masahiro Iida - RankMe

95 papers A 3B 10C 9Misc 4Journal 33Unranked 34

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	Improving Area Efficiency in Synthesizable eFPGA with Multi-output Logic Cell and Domain-Specific Routing Architecture. FPGA Ryo Iwasaki, Tatsuya Sasaki, Yumi Iseki, Sota Kohata, Miyu Yoshida, Kenshu Seto, Masahiro Iida
2025	—	`conf`	Application of Nonvolatile IP with MTJ to eFPGA. NVMSA Keizo Hiraga, Kenshu Seto, Kazuhiro Bessho, Masahiro Iida
2025	—	`conf`	Minimizing Local Interconnections to Reduce Chip Area in eFPGAs. HEART Kenshu Seto, Masahiro Iida
2025	J	`jnl`	Proposal for Non-Volatilization of Logic Cell Architecture for eFPGA IP. IPSJ Trans. Syst. LSI Des. Methodol. Keizo Hiraga, Kenshu Seto, Kazuhiro Bessho, Masahiro Iida
2025	—	`conf`	Proposal for Non-Volatilization of eFPGA Core. COOL CHIPS Keizo Hiraga, Kenshu Seto, Kazuhiro Bessho, Masahiro Iida
2024	J	`jnl`	Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic. IEICE Trans. Inf. Syst. Souhei Takagi, Takuya Kojima, Hideharu Amano, Morihiro Kuga, Masahiro Iida
2024	—	`conf`	SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. COOL CHIPS Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida
2023	J	`jnl`	An eFPGA Generation Suite with Customizable Architecture and IDE. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida
2022	J	`jnl`	A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks. IPSJ Trans. Syst. LSI Des. Methodol. Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida
2022	B	`conf`	FPL Demo: An FPGA-IP Prototype Chip for MEC devices. FPL Morihiro Kuga, Masahiro Iida, Hideharu Amano
2022	J	`jnl`	Reconfigurable Neural Network Accelerator and Simulator for Model Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Qian Zhao, Masahiro Iida
2022	—	`conf`	Towards the Design of Locally Differential Private Hardware System for Edge Computing. CANDAR Kaito Taguchi, Kouichi Sakurai, Masahiro Iida
2021	—	`conf`	Automatic executable code generation for DNN accelerator ReNA. CANDAR (Workshops) Yuta Masuda, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida
2021	—	`conf`	Automation of Domain-specific FPGA-IP Generation and Test. HEART Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga
2021	J	`jnl`	Development of Quantized DNN Library for Exact Hardware Emulation. CoRR Masato Kiyama, Motoki Amagasaki, Masahiro Iida
2020	—	`conf`	A Microcode-based Control Unit for Deep Learning Processors. IPDPS Workshops Qian Zhao, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida
2020	—	`conf`	Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network. CANDAR Qian Zhao, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida
2020	C	`conf`	Image Search System Based on Feature Vectors of Convolutional Neural Network. TENCON Mery Diana, Motoki Amagasaki, Masahiro Iida
2020	J	`jnl`	R-GCN Based Function Inference for Gate-level Netlist. IPSJ Trans. Syst. LSI Des. Methodol. Motoki Amagasaki, Hiroki Oyama, Yuichiro Fujishiro, Masahiro Iida, Hiroaki Yasuda, Hiroto Ito
2020	J	`jnl`	Relationship between Recognition Accuracy and Numerical Precision in Convolutional Neural Network Models. IEICE Trans. Inf. Syst. Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Masahiro Iida
2019	—	`conf`	A Novel SLM-Based Virtual FPGA Overlay Architecture. MCSoC Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Masato Kiyama
2019	—	`conf`	A Quantized Neural Network Library for Proper Implementation of Hardware Emulation. CANDAR Workshops Masato Kiyama, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida
2019	—	`conf`	A Resource Reduced Application-Specific FPGA Switch. ARC Qian Zhao, Yoshimasa Ohnishi, Masahiro Iida, Takaichi Yoshida
2019	J	`jnl`	A SLM-based overlay architecture for fine-grained virtual FPGA. IEICE Electron. Express Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida
2019	—	`conf`	Deep Learning Framework with Arbitrary Numerical Precision. MCSoC Masato Kiyama, Motoki Amagasaki, Masahiro Iida
2018	—	`ch.`	Design Methodology. Principles and Structures of FPGAs Masahiro Iida
2018	J	`jnl`	Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. IEICE Trans. Inf. Syst. Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2018	J	`jnl`	Order Adjustment Approach Using Cayley Graphs for the Order/Degree Problem. IEICE Trans. Inf. Syst. Teruaki Kitasuka, Takayuki Matsuzaki, Masahiro Iida
2018	J	`jnl`	Three Dimensional FPGA Architecture with Fewer TSVs. IEICE Trans. Inf. Syst. Motoki Amagasaki, Masato Ikebe, Qian Zhao, Masahiro Iida, Toshinori Sueyoshi
2018	—	`ch.`	What Is an FPGA? Principles and Structures of FPGAs Masahiro Iida
2017	—	`conf`	A Study of FPGA Virtualization and Accelerator Scheduling. ETCD@ASPLOS Qian Zhao, Masahiro Iida, Toshinori Sueyoshi
2017	—	`conf`	FPGA based ASIC Emulator with High Speed Optical Serial Links. HEART Motoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
2017	—	`conf`	High-level Synthesis based on Parallel Design Patterns using a Functional Language. HEART Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2017	J	`jnl`	Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. IEICE Trans. Inf. Syst. Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2017	J	`jnl`	Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Trans. Syst. LSI Des. Methodol. Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2017	—	`conf`	hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. FPT Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2016	J	`jnl`	A Heuristic Method of Generating Diameter 3 Graphs for Order/Degree Problem. CoRR Teruaki Kitasuka, Masahiro Iida
2016	J	`jnl`	A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2016	—	`conf`	A heuristic method of generating diameter 3 graphs for order/degree problem (invited paper). NOCS Teruaki Kitasuka, Masahiro Iida
2016	C	`conf`	A novel soft error tolerant FPGA architecture. VLSI-SoC Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi
2016	—	`conf`	An area compact soft error resident circuit for FPGA. ICICDT Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi
2016	J	`jnl`	SLM: A Scalable Logic Module Architecture with Less Configuration Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Motoki Amagasaki, Ryo Araki, Masahiro Iida, Toshinori Sueyoshi
2016	—	`conf`	hCODE: An open-source platform for FPGA accelerators. FPT Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	J	`jnl`	A 3D FPGA Architecture to Realize Simple Die Stacking. Inf. Media Technol. Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	J	`jnl`	A 3D FPGA Architecture to Realize Simple Die Stacking. IPSJ Trans. Syst. LSI Des. Methodol. Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	C	`conf`	Architecture exploration of 3D FPGA to minimize internal layer connection. VLSI-SoC Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	J	`jnl`	Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. IEICE Trans. Inf. Syst. Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015	—	`conf`	Simple wafer stacking 3D-FPGA architecture. ICICDT Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2014	B	`conf`	A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. FPL Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2014	—	`conf`	A novel three-dimensional FPGA architecture with high-speed serial communication links. FPT Takuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi
2014	—	`conf`	Blokus Duo engine on a Zynq. FPT Susumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2014	—	`conf`	Zyndroid: An Android platform for software/hardware coprocessing. FPT Susumu Mashimo, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	A	`conf`	A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	J	`jnl`	A reconfigurable Java accelerator with software compatibility for embedded systems. SIGARCH Comput. Archit. News Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
2013	—	`conf`	An FPGA design and implementation framework combined with commercial VLSI CADs. ReCoSoC Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	B	`conf`	An automatic FPGA design and implementation framework. FPL Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	B	`conf`	Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	J	`jnl`	FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	C	`conf`	Three-dimensional stacking FPGA architecture using face-to-face integration. VLSI-SoC Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	—	`conf`	A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration. ICA3PP (1) Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	—	`conf`	A novel physical defects recovery technique for FPGA-IP cores. ReConFig Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	—	`conf`	Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration. FPT Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
2012	J	`jnl`	An Easily Testable Routing Architecture and Prototype Chip. IEICE Trans. Inf. Syst. Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
2012	J	`jnl`	COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. IEICE Trans. Inf. Syst. Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi
2012	Misc	`conf`	Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. FCCM Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	C	`conf`	Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	—	`conf`	Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration. ICA3PP (1) Makoto Fujino, Hiroki Tanaka, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
2012	B	`conf`	Fault detection and avoidance of FPGA in various granularities. FPL Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	J	`jnl`	Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
2011	J	`jnl`	A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. IEICE Trans. Electron. Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
2011	J	`jnl`	A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. IEEE Embed. Syst. Lett. Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2011	—	`conf`	A novel reconfigurable logic device base on 3D stack technology. 3DIC Qian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2011	B	`conf`	An Easily Testable Routing Architecture and Efficient Test Technique. FPL Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2011	C	`conf`	An easily testable routing architecture of FPGA. VLSI-SoC Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi
2011	J	`jnl`	Improving the Soft-error Tolerability of a Soft-core Processor on. J. Next Gener. Inf. Technol. Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2011	J	`jnl`	Parallelization of the channel width search for FPGA routing. SIGARCH Comput. Archit. News Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2010	J	`jnl`	A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. ACM Trans. Reconfigurable Technol. Syst. Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2010	—	`conf`	A robust reconfigurable logic device based on less configuration memory logic cell. FPT Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2010	B	`conf`	COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization. FPL Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2010	B	`conf`	First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. FPL Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
2010	Misc	`conf`	Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. FCCM Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2010	C	`conf`	Power-aware FPGA routing fabrics and design tools. VLSI-SoC Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2009	—	`conf`	A Novel Local Interconnect Architecture for Variable Grain Logic Cell. ARC Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2009	C	`conf`	Improvement of Execution Efficiency on the MX Core. PDCAT Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi
2008	J	`jnl`	An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture. Int. J. Reconfigurable Comput. Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, Toshinori Sueyoshi
2007	Misc	`conf`	A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. FCCM Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi
2007	Misc	`conf`	A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. FCCM Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi
2007	J	`jnl`	A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices. IEICE Trans. Inf. Syst. Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi
2007	B	`conf`	A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. FPL Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi
2007	—	`conf`	An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture. FPT Yoshiaki Satou, Motoki Amagasaki, Hiroshi Miura, Kazunori Matsuyama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi
2007	—	`conf`	Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. ARC Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi
2006	A	`conf`	Effective clustering technique to optimize routability of outer cluster nets. FPGA Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi
2006	C	`conf`	Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device. VLSI-SoC Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi
2005	B	`conf`	Applying the Small-World Network to Routing Structure of FPGAs. FPL Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi
2002	J	`jnl`	Configurable and Reconfigurable Computing for Digital Signal Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshinori Sueyoshi, Masahiro Iida