Masahiro Fujita

111 papers A* 1A 6B 1C 17Misc 7Journal 35Unranked 43

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A comparative study on formal verification techniques to verify large integer multiplier circuits. Integr. Jitendra Kumar, Asutosh Srivastava, Masahiro Fujita
2026	—	`conf`	LA-SCG: Layout-Aware Scan Chain Grouping for Peak Shift Power and IR-Drop Mitigation in Scan-Based Testing. LATS Rohit Badjatya, Harsh Gupta, Makoto Ikeda, Masahiro Fujita, Virendra Singh
2026	—	`conf`	LPCG: A Capture Activity-Aware Technique for Low-Power Scan Testing. LATS Rohit Badjatya, Jaydev Bapat, Makoto Ikeda, Masahiro Fujita, Virendra Singh
2025	J	`jnl`	Breaking the Barriers of One-to-One Usage of Implicit Neural Representation in Image Compression: A Linear Combination Approach With Performance Guarantees. IEEE Internet Things J. Sai Sanjeet, Seyyedali Hosseinalipour, Jinjun Xiong, Masahiro Fujita, Bibhu Datta Sahoo
2025	—	`conf`	Learned Image Codec on FPGA: Algorithm, Architecture and System Design. ASP-DAC Heming Sun, Jing Wang, Silu Liu, Shinji Kimura, Masahiro Fujita
2025	Misc	`conf`	Multi-Object Detection Through Meta-Training in Resource-Constrained UAV-Based Surveillance Applications. VLSID Abhishek Yadav, Vyom Kumar Gupta, Kethireddy Harshith Reddy, Masahiro Fujita, Binod Kumar
2025	J	`jnl`	RefSCAT-2.0: Formal Verification of Large-Scale Optimized Multipliers via Quantum-Inspired Ant Colony Optimization-Based Reference Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rui Li, Lin Li, Heng Yu, Masahiro Fujita, Weixiong Jiang, Yajun Ha
2025	J	`jnl`	RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rui Li, Lin Li, Heng Yu, Masahiro Fujita, Weixiong Jiang, Yajun Ha
2025	—	`conf`	Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation Approximation. ISVLSI Abhishek Yadav, Ayush Dixit, Utsav Jana, Masahiro Fujita, Binod Kumar
2025	J	`jnl`	Systematic Design of Ring VCO-Based SNN - Translating Training Parameters to Circuits. IEEE Open J. Circuits Syst. Sai Sanjeet, Sanchari Das, Shiuh-Hua Wood Chiang, Masahiro Fujita, Bibhu Datta Sahoo
2025	—	`conf`	Weight-Aware Scan Chain Stitching for Shift Power Minimization under Routing Constraints. ATS Rohit Badjatya, Kapil Sharma, Makoto Ikeda, Masahiro Fujita, Virendra Singh
2024	J	`jnl`	Bidirectional LSTM Model for Accurate and Real-Time Landslide Detection: A Case Study in Mawiongrim, Meghalaya, India. IEEE Internet Things J. J. Sharailin Gidon, Jintu Borah, Smrutirekha Sahoo, Shubhankar Majumdar, Masahiro Fujita
2024	J	`jnl`	FPGA Codec System of Learned Image Compression With Algorithm-Architecture Co-Optimization. IEEE J. Emerg. Sel. Topics Circuits Syst. Heming Sun, Qingyang Yi, Masahiro Fujita
2024	—	`conf`	LLM-aided Front-End Design Framework For Early Development of Verified RTLs. ATS Vyom Kumar Gupta, Abhishek Yadav, Masahiro Fujita, Binod Kumar
2024	—	`conf`	Lightweight DL-based Drone Image Classification for Surveillance Applications. ISOCC Abhishek Yadav, Masahiro Fujita, Binod Kumar
2024	—	`conf`	Physical-Design Aware Scan Cell Reordering for Low Power Testing. EWDTS Rohit Badjatya, N. S. Vinay, Rahul Kumar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2024	—	`conf`	Resource-efficient DL Model Inference with Weight Clustering and Zero-skipping. ISOCC Abhishek Yadav, Masahiro Fujita, Binod Kumar
2024	—	`conf`	Systematic Design of Ring VCO-Based SNN - Translating Training Parameters to Circuits -. MWSCAS Sai Sanjeet, Sanchari Das, Shiuh-Hua Wood Chiang, Masahiro Fujita, Bibhu Datta Sahoo
2023	J	`jnl`	Energy-Efficient FPGA Implementation of Power-of-2 Weights-Based Convolutional Neural Networks With Low Bit-Precision Input Images. IEEE Trans. Circuits Syst. II Express Briefs Sai Sanjeet, Bibhu Datta Sahoo, Masahiro Fujita
2023	J	`jnl`	Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jitendra Kumar, Yukio Miyasaka, Asutosh Srivastava, Masahiro Fujita
2023	C	`conf`	IIR Filter-Based Spiking Neural Network. ISCAS Sai Sanjeet, Rahul K. Meena, Bibhu Datta Sahoo, Keshab K. Parhi, Masahiro Fujita
2023	—	`conf`	LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error. LATS Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh
2023	—	`conf`	Noise Resilience of Reduced Precision Neural Networks. HEART Sai Sanjeet, Sannidhi Boppana, Bibhu Datta Sahoo, Masahiro Fujita
2023	—	`conf`	Optimization of Imprecise Multiplier Circuits by using Binary Decision Diagram. iSES Pooja Choudhary, Lava Bhargava, G. U. Vinod, Ashok Kumar Suhag, Masahiro Fujita, Virendra Singh
2022	J	`jnl`	Approximating Arithmetic Circuits for IoT Devices Data Processing. Comput. Ind. Eng. Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh, Ashok Kumar Suhag
2022	J	`jnl`	Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Binod Kumar, V. S. Vineesh, Puneet Nemade, Masahiro Fujita
2022	J	`jnl`	BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature. IEEE Trans. Very Large Scale Integr. Syst. Ying Zhang, Yi Ding, Zebo Peng, Huawei Li, Masahiro Fujita, Jianhui Jiang
2022	—	`conf`	Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing Test. ATS Utsav Jana, Sourav Banerjee, Binod Kumar, Madhu B, Shankar Umapathi, Masahiro Fujita
2022	J	`jnl`	High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing. IEEE Trans. Circuits Syst. I Regul. Pap. Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
2022	—	`conf`	Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. VDAT Anishetti Venkatesh, Chandan Kumar Jha, G. U. Vinod, Masahiro Fujita, Virendra Singh
2022	—	`conf`	Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. VDAT Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh
2021	J	`jnl`	Design of Single-Bit Fault-Tolerant Reversible Circuits. IEEE Des. Test Hari Mohan Gaur, Ashutosh Kumar Singh, Anand Mohan, Masahiro Fujita, Dhiraj K. Pradhan
2021	J	`jnl`	Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. V. S. Vineesh, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, Virendra Singh
2021	A	`conf`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2021	J	`jnl`	SAT-Based On-Track Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. He-Teng Zhang, Masahiro Fujita, Chung-Kuan Cheng, Jie-Hong R. Jiang
2020	J	`jnl`	A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters. IEEE Trans. Circuits Syst. Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
2020	J	`jnl`	A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality. IPSJ Trans. Syst. LSI Des. Methodol. Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita
2020	Misc	`conf`	A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. VLSID Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh
2020	J	`jnl`	A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. Binod Kumar, Jay Adhaduk, Kanad Basu, Masahiro Fujita, Virendra Singh
2020	J	`jnl`	An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita
2020	—	`conf`	LUT-based Circuit Approximation with Targeted Error Guarantees. ATS Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2020	J	`jnl`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2020	J	`jnl`	Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
2020	—	`conf`	Real-Time Threshold-based Landslide Prediction System for Hilly Region using Wireless Sensor Networks. ICCE-TW Kamal Das, Shubhankar Majumdar, Soumen Moulik, Masahiro Fujita
2020	—	`conf`	Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints. ISQED Akihiro Goda, Yukio Miyasaka, Amir Masoud Gharehbaghi, Masahiro Fujita
2020	A	`conf`	Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations. DATE Masahiro Fujita, Yusuke Kimura, Xingming Le, Yukio Miyasaka, Amir Masoud Gharehbaghi
2020	J	`jnl`	Theoretical Analysis of Noise Figure for Modulated Wideband Converter. IEEE Trans. Circuits Syst. I Regul. Pap. Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
2019	Misc	`conf`	A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. VLSID Binod Kumar, Masahiro Fujita, Virendra Singh
2019	—	`conf`	Adder-Only Convolutional Neural Network with Binary Input Image. MWSCAS Mayank Palaria, Sai Sanjeet, Bibhu Datta Sahoo, Masahiro Fujita
2019	Misc	`conf`	An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults. VTS Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita
2019	C	`conf`	Approximate Arithmetic Circuit Design Using a Fast and Scalable Method. VLSI-SoC Qi Lu, Amir Masoud Gharehbaghi, Masahiro Fujita
2019	J	`jnl`	Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita
2019	—	`conf`	Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults. ISQED Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita
2019	C	`conf`	High-Level Engineering Change Through Programmable Datapath and SMT Solvers. ISCAS Qinhao Wang, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita
2019	C	`conf`	Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints. ISCAS Tomohiro Maruoka, Yukio Miyasaka, Akihiro Goda, Amir Masoud Gharehbaghi, Masahiro Fujita
2019	—	`conf`	Preventing Scan Attack through Test Response Encryption. DFT Satyadev Ahlawat, Jaynarayan T. Tudu, Manoj Singh Gaur, Masahiro Fujita, Virendra Singh
2019	J	`jnl`	SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. J. Electron. Test. Binod Kumar, Masahiro Fujita, Virendra Singh
2019	C	`conf`	Securing Scan through Plain-text Restriction. IOLTS Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2019	J	`jnl`	Signal Selection Methods for Debugging Gate-Level Sequential Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita
2019	C	`conf`	Signal Selection Methods for Efficient Multi-Target Correction. ISCAS Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita
2019	—	`ed.`	VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers VLSI-SoC (Selected Papers) Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd M. Austin, Ricardo Reis
2019	—	`conf`	Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. ATS Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita, Virendra Singh
2018	—	`conf`	A New Reconfigurable Architecture with Applications to IoT and Mobile Computing. IFIPIoT@WCC Amir Masoud Gharehbaghi, Tomohiro Maruoka, Masahiro Fujita
2018	J	`jnl`	An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults. IEEE Trans. Circuits Syst. I Regul. Pap. Peikun Wang, Conrad J. Moore, Amir Masoud Gharehbaghi, Masahiro Fujita
2018	J	`jnl`	C Description Reconstruction Method from a Revised Netlist for ECO Support. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita
2018	Misc	`conf`	ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. VLSID Ankit Jindal, Binod Kumar, Kanad Basu, Masahiro Fujita
2018	J	`jnl`	Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. J. Electron. Test. Toral Shah, Anzhela Yu. Matrosova, Masahiro Fujita, Virendra Singh
2018	C	`conf`	On Securing Scan Design Through Test Vector Encryption. ISCAS Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2018	—	`conf`	Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. ISVLSI Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita, Virendra Singh
2017	—	`conf`	A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. VDAT Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita
2017	Misc	`conf`	A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. VLSID Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita
2017	C	`conf`	A low-cost approximate 32-point transform architecture. ISCAS Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita
2017	C	`conf`	A new approach for constructing logic functions after ECO. VLSI-SoC Amir Masoud Gharehbaghi, Masahiro Fujita
2017	C	`conf`	A new approach for diagnosing bridging faults in logic designs. ISCAS Amir Masoud Gharehbaghi, Masahiro Fujita
2017	—	`conf`	A new approach for selecting inputs of logic functions during debug. ISQED Amir Masoud Gharehbaghi, Masahiro Fujita
2017	—	`conf`	Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. ACM Great Lakes Symposium on VLSI Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh
2017	C	`conf`	Improving post-silicon error detection with topological selection of trace signals. VLSI-SoC Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh
2017	—	`conf`	Post Silicon Debugging of Electrical Bugs Using Trace Buffers. ATS Kentaro Iwata, Amir Masoud Gharehbaghi, Mehdi Baradaran Tahoori, Masahiro Fujita
2017	—	`conf`	Post-silicon observability enhancement with topology based trace signal selection. LATS Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh
2017	—	`conf`	RTL level trace signal selection and coverage estimation during post-silicon validation. HLDVT Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
2017	C	`conf`	Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults. ISCAS Conrad J. Moore, Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita
2017	—	`conf`	Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh
2016	—	`conf`	A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality. ATS Amir Masoud Gharehbaghi, Masahiro Fujita
2016	J	`jnl`	Fast and Efficient Signature-Based Sub-Circuit Matching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Amir Masoud Gharehbaghi, Masahiro Fujita
2015	C	`conf`	Efficient signature-based sub-circuit matching. VLSI-SoC Amir Masoud Gharehbaghi, Masahiro Fujita
2015	A	`conf`	Temperature-aware software-based self-testing for delay faults. DATE Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro Fujita
2015	C	`conf`	Trace signal selection methods for post silicon debugging. VLSI-SoC Shridhar Choudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita
2014	J	`jnl`	Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model. IEICE Trans. Inf. Syst. Amir Masoud Gharehbaghi, Masahiro Fujita
2014	—	`conf`	Specification and formal verification of power gating in processors. ISQED Amir Masoud Gharehbaghi, Masahiro Fujita
2013	—	`conf`	Debugging processors with advanced features by reprogramming LUTs on FPGA. FPT Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita
2013	—	`conf`	Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing. FPT Will X. Y. Li, Shridhar Chaudhary, Ray C. C. Cheung, Takeshi Matsumoto, Masahiro Fujita
2013	J	`jnl`	On the integration of model-driven design and dynamic assertion-based verification for embedded software. J. Syst. Softw. Giuseppe Di Guglielmo, Luigi Di Guglielmo, Andreas Foltinek, Masahiro Fujita, Franco Fummi, Cristina Marconcini, Graziano Pravadelli
2013	A	`conf`	Rectification of advanced microprocessors without changing routing on FPGAs (abstract only). FPGA Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita
2012	—	`conf`	Automatic rectification of design errors in complex processors with programmable hardware. FPT Amir Masoud Gharehbaghi, Masahiro Fujita
2012	Misc	`conf`	Dynamic property mining for embedded software. CODES+ISSS Marco Bonato, Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli
2012	—	`conf`	Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods. Asian Test Symposium Amir Masoud Gharehbaghi, Masahiro Fujita
2012	J	`jnl`	Time-Constraint-Aware Optimization of Assertions in Embedded Software. J. Electron. Test. Viacheslav Izosimov, Giuseppe Di Guglielmo, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Masahiro Fujita
2012	J	`jnl`	Transaction Ordering in Network-on-Chips for Post-Silicon Validation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Amir Masoud Gharehbaghi, Masahiro Fujita
2012	—	`conf`	Transaction-based post-silicon debug of many-core System-on-Chips. ISQED Amir Masoud Gharehbaghi, Masahiro Fujita
2011	C	`conf`	EFSM-based model-driven approach to concolic testing of system-level design. MEMOCODE Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli, Stefano Soffia
2011	—	`conf`	Formal verification guided automatic design error diagnosis and correction of complex processors. HLDVT Amir Masoud Gharehbaghi, Masahiro Fujita
2011	—	`conf`	Global transaction ordering in Network-on-Chips for post-silicon validation. ISQED Amir Masoud Gharehbaghi, Masahiro Fujita
2011	—	`conf`	Model-driven design and validation of embedded software. AST@ICSE Giuseppe Di Guglielmo, Masahiro Fujita, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli, Cristina Marconcini, Andreas Foltinek
2011	B	`conf`	Optimization of Assertion Placement in Time-Constrained Embedded Systems. ETS Viacheslav Izosimov, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Giuseppe Di Guglielmo, Masahiro Fujita
2010	A	`conf`	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). FPGA Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita
2010	—	`conf`	Pipelined Microprocessors Optimization and Debugging. ARC Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita
2009	A*	`conf`	Debugging from high level down to gate level. DAC Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi
2009	C	`conf`	Transaction-based debugging of system-on-chips with patterns. ICCD Amir Masoud Gharehbaghi, Masahiro Fujita
1996	J	`jnl`	Solving the net matching problem in high-performance chip design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi
1995	C	`conf`	Simple tree-construction heuristics for the fanout problem . ICCD Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng
1993	A	`conf`	An efficient algorithm for the net matching problem. ICCAD Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita