Masahiro Fujita

373 papers A* 27A 35B 10C 46Misc 22Journal 86Unranked 144

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Psychological features of dispute content and public acceptance of AI in legal adjudication: evidence for systematic variation beyond individual differences. Frontiers Artif. Intell. Masahiro Fujita, Eiichiro Watamura
2024	—	`conf`	Accelerating Decision Diagram-based Multi-node Quantum Simulation with Ring Communication and Automatic SWAP Insertion. QSW Yusuke Kimura, Shaowen Li, Hiroyuki Sato, Masahiro Fujita
2024	J	`jnl`	Accelerating Decision Diagram-based Multi-node Quantum Simulation with Ring Communication and Automatic SWAP Insertion. CoRR Yusuke Kimura, Shaowen Li, Hiroyuki Sato, Masahiro Fujita
2024	Misc	`conf`	Decision Diagram vs. State Vector: A Comparative Study on Quantum Computing Simulation Efficiency. QCE Yusuke Kimura, Shaowen Li, Hiroyuki Sato, Masahiro Fujita
2024	—	`conf`	Multi-Observed Authentication: A secure and usable authentication based on multi-point observation of a single physical credential. APSIPA Wataru Hatakeyama, Shinnosuke Nozaki, Ayumi Serizawa, Mizuho Yoshihira, Masahiro Fujita, Ayako Yoshimura, Tetsushi Ohki, Masakatsu Nishigaki
2023	—	`conf`	Parallelizing quantum simulation with decision diagrams. QSW Shaowen Li, Yusuke Kimura, Hiroyuki Sato, Junwei Yu, Masahiro Fujita
2023	J	`jnl`	Parallelizing quantum simulation with decision diagrams. CoRR Shaowen Li, Yusuke Kimura, Hiroyuki Sato, Junwei Yu, Masahiro Fujita
2022	—	`conf`	Formal Analysis of Integer Multipliers by building Binary Decision Diagram of Adder Trees. ISQED Jitendra Kumar, Asutosh Srivastava, Masahiro Fujita
2022	—	`conf`	Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT Models. ISQED Xinpei Zhang, Yi Ding, Mingfei Yu, Shin-ichi O'Uchi, Masahiro Fujita
2022	—	`conf`	Multi-observed Multi-factor Authentication: A Multi-factor Authentication Using Single Credential. NBiS Shinnosuke Nozaki, Ayumi Serizawa, Mizuho Yoshihira, Masahiro Fujita, Yoichi Shibata, Tadakazu Yamanaka, Nori Matsuda, Tetsushi Ohki, Masakatsu Nishigaki
2022	J	`jnl`	Parallel Scheduling Attention Mechanism: Generalization and Optimization. IPSJ Trans. Syst. LSI Des. Methodol. Mingfei Yu, Yukio Miyasaka, Masahiro Fujita
2022	J	`jnl`	Proposal of anonymization dictionary using disclosed statements by business operators. Internet Things Masahiro Fujita, Yasuoki Iida, Mitsuhiro Hattori, Tadakazu Yamanaka, Nori Matsuda, Satoshi Ito, Hiroaki Kikuchi
2022	C	`conf`	Real-time Learned Image Codec on FPGA. VCIP Heming Sun, Qingyang Yi, Fangzheng Lin, Lu Yu, Jiro Katto, Masahiro Fujita
2021	—	`conf`	A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication Structure. ASP-DAC Mingfei Yu, Ruitao Gao, Masahiro Fujita
2021	—	`conf`	Efficient Reachability Analysis Based on Inductive Invariant Using X-value Based Flipflop Selection. ISQED Ryogo Koikel, Masahiro Fujita
2021	J	`jnl`	FPGA Based Accelerator for Neural Networks Computation with Flexible Pipelining. CoRR Qingyang Yi, Heming Sun, Masahiro Fujita
2021	A	`conf`	Logic Synthesis for Generalization and Learning Addition. DATE Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita
2021	—	`conf`	Proposal and Development of Anonymization Dictionary Using Public Information Disclosed by Anonymously Processed Information Handling Business Operators. IMIS Masahiro Fujita, Yasuoki Iida, Mitsuhiro Hattori, Tadakazu Yamanaka, Nori Matsuda, Satoshi Ito, Hiroaki Kikuchi
2021	—	`conf`	Web Crawler for an Anonymously Processed Information Database. IMIS Hiroaki Kikuchi, Atsuki Ono, Satoshi Ito, Masahiro Fujita, Tadakazu Yamanaka
2020	J	`jnl`	Development and field test of the articulated mobile robot T2 Snake-4 for plant disaster prevention. Adv. Robotics Motoyasu Tanaka, Kazuyuki Kon, Mizuki Nakajima, Nobutaka Matsumoto, Shinnosuke Fukumura, Kosuke Fukui, Hidemasa Sawabe, Masahiro Fujita, Kenjiro Tadakuma
2020	J	`jnl`	Development of a folding arm on an articulated mobile robot for plant disaster prevention. Adv. Robotics Nobutaka Matsumoto, Motoyasu Tanaka, Mizuki Nakajima, Masahiro Fujita, Kenjiro Tadakuma
2020	J	`jnl`	HIVE: A cross-platform, modular visualization framework for large-scale data sets. Future Gener. Comput. Syst. Kenji Ono, Jorji Nonaka, Tomohiro Kawanabe, Masahiro Fujita, Kentaro Oku, Kazuma Hatta
2020	B	`conf`	Micro Biometric Authentication Using Fingernail Surfaces: A Study of Practical Use. AINA Yuya Shiomi, Genki Sugimoto, Ayaka Sugimoto, Kota Uehara, Masahiro Fujita, Yuto Mano, Tetsushi Ohki, Masakatsu Nishigaki
2020	J	`jnl`	Parallel Scheduling Self-attention Mechanism: Generalization and Optimization. CoRR Mingfei Yu, Masahiro Fujita
2020	C	`conf`	SAT-Based Data-Flow Mapping Onto Array Processor. VLSI-SOC Yukio Miyasaka, Masahiro Fujita
2020	—	`conf`	SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. VLSI-SoC (Selected Papers) Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek
2020	J	`jnl`	Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication. IPSJ Trans. Syst. LSI Des. Methodol. Yukio Miyasaka, Akihiro Goda, Ashish Mittal, Masahiro Fujita
2020	—	`conf`	Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing. ATS Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
2020	J	`jnl`	What are the important technologies for bin picking? Technology analysis of robots in competitions based on a set of performance metrics. Adv. Robotics Masahiro Fujita, Yukiyasu Domae, Akio Noda, Gustavo Alfonso Garcia Ricardez, Tatsuya Nagatani, Andy Zeng, Shuran Song, Alberto Rodriguez, Albert J. Causo, I-Ming Chen, Tsukasa Ogasawara
2019	—	`conf`	A 48 MHz 880-nW Standby Power Normally-Off MCU with 1 Clock Full Backup and 4.69-μs Wakeup Featuring 60-nm Crystalline In-Ga-Zn Oxide BEOL-FETs. VLSI Circuits Takahiko Ishizu, Yuto Yakubo, Kazuma Furutani, Atsuo Isobe, Masashi Fujita, Tomoaki Atsumi, Yoshinori Ando, Tsutomu Murakawa, Kiyoshi Kato, Masahiro Fujita, Shunpei Yamazaki
2019	—	`conf`	AI x Robotics: Technology Challenges and Opportunities in Sensors, Actuators, and Integrated Circuits. ISSCC Masahiro Fujita
2019	B	`conf`	Basic Study on Targeted E-mail Attack Method Using OSINT. AINA Kota Uehara, Kohei Mukaiyama, Masahiro Fujita, Hiroki Nishikawa, Takumi Yamamoto, Kiyoto Kawauchi, Masakatsu Nishigaki
2019	—	`conf`	Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions. ISPD Masahiro Fujita
2019	—	`conf`	Bin-picking Robot using a Multi-gripper Switching Strategy based on Object Sparseness. CASE Masahiro Fujita, Yukiyasu Domae, Ryosuke Kawanishi, Gustavo Alfonso Garcia Ricardez, Kenta Kato, Koji Shiratsuchi, Rintaro Haraguchi, Ryosuke Araki, Hironobu Fujiyoshi, Shuichi Akizuki, Manabu Hashimoto, Albert J. Causo, Akio Noda, Haruhisa Okuda, Tsukasa Ogasawara
2019	J	`jnl`	Data-path aware high-level ECO synthesis. Integr. Masoud Shiroei, Bijan Alizadeh, Masahiro Fujita
2019	—	`ch.`	Development of Tough Snake Robot Systems. Disaster Robotics Fumitoshi Matsuno, Tetsushi Kamegawa, Wei Qi, Tatsuya Takemori, Motoyasu Tanaka, Mizuki Nakajima, Kenjiro Tadakuma, Masahiro Fujita, Yosuke Suzuki, Katsutoshi Itoyama, Hiroshi G. Okuno, Yoshiaki Bando, Tomofumi Fujiwara, Satoshi Tadokoro
2019	—	`conf`	Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing. ISQED Yukio Miyasaka, Ashish Mittal, Masahiro Fujita
2019	J	`jnl`	Task-Space Control of Articulated Mobile Robots With a Soft Gripper for Operations. IEEE Trans. Robotics Motoyasu Tanaka, Kenjiro Tadakuma, Mizuki Nakajima, Masahiro Fujita
2018	J	`jnl`	234Compositor: A flexible parallel image compositing framework for massively parallel visualization environments. Future Gener. Comput. Syst. Jorji Nonaka, Kenji Ono, Masahiro Fujita
2018	—	`conf`	A 20ns-write 45ns-read and 10 ISSCC Shuhei Maeda, Satoru Ohshita, Kazuma Furutani, Yuto Yakubo, Takahiko Ishizu, Tomoaki Atsumi, Yoshinori Ando, Daisuke Matsubayashi, Kiyoshi Kato, Takashi Okuda, Masahiro Fujita, Shunpei Yamazaki
2018	—	`conf`	A Large Data Visualization Framework for SPARC64 fx HPC Systems - Case Study: K Computer Operational Environment -. LDAV Jorji Nonaka, Kenji Ono, Naohisa Sakamoto, Kengo Hayashi, Motohiko Matsuda, Fumiyoshi Shoji, Kentaro Oku, Masahiro Fujita, Kazuma Hatta
2018	C	`conf`	A Study on Open Source Software for Large-Scale Data Visualization on SPARC64fx based HPC Systems. HPC Asia Jorji Nonaka, Motohiko Matsuda, Takashi Shimizu, Naohisa Sakamoto, Masahiro Fujita, Keiji Onishi, Eduardo C. Inacio, Shun Ito, Fumiyoshi Shoji, Kenji Ono
2018	J	`jnl`	Development and Testing of Force-Sensing Forceps Using FBG for Bilateral Micro-Operation System. IEEE Robotics Autom. Lett. Hiroyuki Suzuki, Hiromasa Masuda, Kazuo Hongo, Ryuta Horie, Shunsuke Yajima, Yuki Itotani, Masahiro Fujita, Ken'ichiro Nagasaka
2018	J	`jnl`	Development of universal vacuum gripper for wall-climbing robot. Adv. Robotics Masahiro Fujita, Suguru Ikeda, Toshiaki Fujimoto, Toshihiko Shimizu, Shuhei Ikemoto, Takeshi Miyamoto
2018	J	`jnl`	Jamming layered membrane gripper mechanism for grasping differently shaped-objects without excessive pushing force for search and rescue missions. Adv. Robotics Masahiro Fujita, Kenjiro Tadakuma, Hirone Komatsu, Eri Takane, Akito Nomura, Tomoya Ichimura, Masashi Konyo, Satoshi Tadokoro
2018	—	`conf`	Memory-system requirements for convolutional neural networks. MEMSYS Antara Ganguly, Virendra Singh, Rajeev Muralidhar, Masahiro Fujita
2018	—	`conf`	Micro Disposable Biometric Authentication: An Application Using Fingernail Minute Textures for Nonsensitive Services. ICBSP Genki Sugimoto, Masahiro Fujita, Yuto Mano, Tetsushi Ohki, Masakatsu Nishigaki
2018	J	`jnl`	Planar Omnidirectional Crawler Mobile Mechanism - Development of Actual Mechanical Prototype and Basic Experiments. IEEE Robotics Autom. Lett. Kenjiro Tadakuma, Eri Takane, Masahiro Fujita, Akito Nomura, Hirone Komatsu, Masashi Konyo, Satoshi Tadokoro
2017	—	`conf`	An approach to approximate computing: Logic transformations for one-minterm changes in specification. HLDVT Masahiro Fujita
2017	—	`conf`	DNetSpec: A Distributed Network Testing Toolset for Middleware Developers. COMPSAC (2) Shintaro Ishihara, Masahiro Fujita, Toyokazu Akiyama
2017	—	`conf`	Directcha-maze: A Study of CAPTCHA Configuration with Machine Learning and Brute-Force Attack Defensibility Along with User Convenience Consideration. BWCCA Ayane Sano, Masahiro Fujita, Masakatsu Nishigaki
2017	—	`conf`	Dissemination of edge-heavy data on heterogeneous MQTT brokers. CloudNet Ryohei Banno, Jingyu Sun, Masahiro Fujita, Susumu Takeuchi, Kazuyuki Shudo
2017	—	`conf`	Distributed Particle-Based Rendering Framework for Large Data Visualization on HPC Environments. HPCS Jorji Nonaka, Naohisa Sakamoto, Takashi Shimizu, Masahiro Fujita, Kenji Ono, Koji Koyamada
2017	J	`jnl`	Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS. IEEE J. Solid State Circuits Tatsuya Onuki, Wataru Uesugi, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, Tri Rung Yew, J. Y. Wu, Chi Chang Shuai, Shao Hui Wu, James Myers, Klaus Doppler, Masahiro Fujita, Shunpei Yamazaki
2017	C	`conf`	Instruction-based self-test for delay faults maximizing operating temperature. IOLTS Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh
2017	—	`conf`	Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs. ISQED Qinhao Wang, Yusuke Kimura, Masahiro Fujita
2017	Misc	`conf`	On Testing of Superscalar Processors in Functional Mode for Delay Faults. VLSID Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh
2017	—	`conf`	Slyware Prevention: Threat of Websites Inducing Accidental Taps and Countermeasures. NBiS Kohei Mukaiyama, Masahiro Fujita, Takeharu Shirai, Shinya Kobayashi, Masakatsu Nishigaki
2017	J	`jnl`	Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch. IEEE Trans. Very Large Scale Integr. Syst. Munehiro Kozuma, Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Makoto Ikeda, Masahiro Fujita, Shunpei Yamazaki
2017	—	`conf`	Systematic approximate logic optimization using don't care conditions. ISQED Sahand Salamat, Mehrnaz Ahmadi, Bijan Alizadeh, Masahiro Fujita
2017	C	`conf`	Template based synthesis for high performance computing. VLSI-SoC Masahiro Fujita, Yusuke Kimura, Qinhao Wang
2016	—	`conf`	A Micro Biometric Authentication Mechanism Considering Minute Patterns of the Human Body: A Proposal and the First Attempt. NBiS Masahiro Fujita, Yuto Mano, Takuya Kaneko, Kenta Takahashi, Masakatsu Nishigaki
2016	—	`conf`	Automatically adjusting system level designs after RTL/gate-level ECO. HLDVT Qinhao Wang, Yusuke Kimura, Masahiro Fujita
2016	C	`conf`	Directcha: A proposal of spatiometric mental rotation CAPTCHA. PST Ayane Sano, Masahiro Fujita, Masakatsu Nishigaki
2016	—	`conf`	Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS. VLSI Circuits Tatsuya Onuki, Wataru Uesugi, Hikaru Tamura, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, Tri Rung Yew, Chen Bin Lin, J. Y. Wu, Chi Chang Shuai, Shao Hui Wu, James Myers, Klaus Doppler, Masahiro Fujita, Shunpei Yamazaki
2016	—	`conf`	Formally analyzing fault tolerance in datapath designs using equivalence checking. ASP-DAC Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita
2016	—	`conf`	Implementation and Initial Evaluation of Game in Which Password Enhancement Factor is Embedded. HCI (26) Masahiro Fujita, Mako Yamada, Masakatsu Nishigaki
2016	—	`conf`	Secure Communication Protocol Between a Human and a Bank Server for Preventing Man-in-the-Browser Attacks. HCI (20) Takashi Tsuchiya, Masahiro Fujita, Kenta Takahashi, Takehisa Kato, Fumihiko Magata, Yoshimi Teshigawara, Ryôichi Sasaki, Masakatsu Nishigaki
2016	—	`conf`	Specification by existing design plus use-cases. HLDVT Yusuke Kimura, Masahiro Fujita
2016	C	`conf`	Study on relationship between user awareness and QoE in communication delay on smartphones. PST Takeharu Shirai, Masahiro Fujita, Daisuke Arai, Tomohiko Ogishi, Masakatsu Nishigaki
2016	B	`conf`	Synthesizing and Completely Testing Hardware Based on Templates Through Small Numbers of Test Patterns. ATVA Masahiro Fujita
2016	—	`conf`	Two axes orthogonal drive transmission for omnidirectional crawler with surface contact. SSRR Eri Takane, Kenjiro Tadakuma, Masahiro Fujita, Hirone Komatsu, Akito Nomura, Tomoya Ichimura, Tomonari Yamamoto, Yuichi Ambe, Masashi Konyo, Satoshi Tadokoro
2016	—	`conf`	Variable inner volume mechanism for soft and robust gripping - Improvement of gripping performance for large-object gripping. SSRR Masahiro Fujita, Kenjiro Tadakuma, Eri Takane, Tomoya Ichimura, Hirone Komatsu, Akito Nomura, Masashi Konyo, Satoshi Tadokoro
2015	—	`conf`	16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using Vt, cancel write method. ISSCC Takanori Matsuzaki, Tatsuya Onuki, Shuhei Nagatsuka, Hiroki Inoue, Takahiko Ishizu, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Masayuki Sakakura, Tomoaki Atsumi, Yutaka Shionoiri, Kiyoshi Kato, Takashi Okuda, Yoshitaka Yamamoto, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki
2015	—	`conf`	234 scheduling of 3-2 and 2-1 eliminations for parallel image compositing using non-power-of-two number of processes. HPCS Jorji Nonaka, Kenji Ono, Masahiro Fujita
2015	J	`jnl`	A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology. IEEE Trans. Very Large Scale Integr. Syst. Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Masataka Ikeda, Munehiro Kozuma, Takeshi Osada, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki
2015	—	`conf`	An Attempt to Memorize Strong Passwords while Playing Games. NBiS Masahiro Fujita, Mako Yamada, Shiori Arimura, Yuki Ikeya, Masakatsu Nishigaki
2015	C	`conf`	Analysis and testing on delays with two time frames. VLSI-SoC Masahiro Fujita
2015	J	`jnl`	Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. IEEE Trans. Computers Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
2015	C	`conf`	Automatic identification of assertions and invariants with small numbers of test vectors. ICCD Masahiro Fujita
2015	—	`conf`	Chimera CAPTCHA: A Proposal of CAPTCHA Using Strangeness in Merged Objects. HCI (22) Masahiro Fujita, Yuki Ikeya, Junya Kani, Masakatsu Nishigaki
2015	—	`conf`	Delay Testing Based on Multiple Faulty Behaviors. VLSI-SoC (Selected Papers) Masahiro Fujita
2015	—	`conf`	Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification. ATS Masahiro Fujita
2015	J	`jnl`	Direct simulation of drying colloidal suspension on substrate using immersed free surface model. J. Comput. Phys. Masahiro Fujita, Osamu Koike, Yukio Yamaguchi
2015	A	`conf`	Hardware in loop testing of an insulin pump. ITC Sriram Karunagaran, Karuna P. Sahoo, Masahiro Fujita
2015	—	`conf`	Incremental ATPG methods for multiple faults under multiple fault models. ISQED Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan Mishchenko
2015	C	`conf`	Logic analysis and optimization with quick identification of invariants through one time frame analysis. MEMOCODE Masahiro Fujita
2015	J	`jnl`	Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register. IEEE J. Solid State Circuits Takeshi Aoki, Yuki Okamoto, Takashi Nakagawa, Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki
2015	A	`conf`	On Implementation of LUT with Large Numbers of Inputs (Abstract Only). FPGA Masahiro Fujita
2015	C	`conf`	Physical trust-based persistent authentication. PST Masahiro Fujita, Christian Damsgaard Jensen, Shiori Arimura, Yuki Ikeya, Masakatsu Nishigaki
2015	J	`jnl`	Toward Unification of Synthesis and Verification in Topologically Constrained Logic Design. Proc. IEEE Masahiro Fujita
2015	Misc	`conf`	UPF-based formal verification of low power techniques in modern processors. VTS Reza Sharafinejad, Bijan Alizadeh, Masahiro Fujita
2014	—	`conf`	30.9 Normally-off computing with crystalline InGaZnO-based FPGA. ISSCC Takeshi Aoki, Yuki Okamoto, Takashi Nakagawa, Masataka Ikeda, Munehiro Kozuma, Takeshi Osada, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki
2014	—	`conf`	A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor. VLSIC Atsuo Isobe, Hikaru Tamura, Kiyoshi Kato, Takuro Ohmaru, Wataru Uesugi, Takahiko Ishizu, Tatsuya Onuki, Kazuaki Ohshima, Takanori Matsuzaki, Atsushi Hirose, Yasutaka Suzuki, Naoaki Tsutsui, Tomoaki Atsumi, Yutaka Shionoiri, Gensuke Goto, Jun Koyama, Masahiro Fujita, Shunpei Yamazaki
2014	J	`jnl`	An Energy-Efficient Patchable Accelerator and Its Design Methods. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Yoshida, Masayuki Wakizaka, Shigeru Yamashita, Masahiro Fujita
2014	—	`conf`	An Image-Based CAPTCHA Using Sophisticated Mental Rotation. HCI (24) Yuki Ikeya, Masahiro Fujita, Junya Kani, Yuta Yoneyama, Masakatsu Nishigaki
2014	A	`conf`	Efficient SAT-based ATPG techniques for all multiple stuck-at faults. ITC Masahiro Fujita, Alan Mishchenko
2014	J	`jnl`	Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor. IEEE Micro Hikaru Tamura, Kiyoshi Kato, Takahiko Ishizu, Wataru Uesugi, Atsuo Isobe, Naoaki Tsutsui, Yasutaka Suzuki, Yutaka Okazaki, Yukio Maehashi, Jun Koyama, Yoshitaka Yamamoto, Shunpei Yamazaki, Masahiro Fujita, James Myers, Pekka Korpinen
2014	—	`conf`	Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating. COOL Chips Hikaru Tamura, Kiyoshi Kato, Takahiko Ishizu, Tatsuya Onuki, Wataru Uesugi, Takuro Ohmaru, Kazuaki Ohshima, Hidetomo Kobayashi, Seiichi Yoneda, Atsuo Isobe, Naoaki Tsutsui, Suguru Hondo, Yasutaka Suzuki, Yutaka Okazaki, Tomoaki Atsumi, Yutaka Shionoiri, Yukio Maehashi, Gensuke Goto, Masahiro Fujita, James Myers, Pekka Korpinen, Jun Koyama, Yoshitaka Yamamoto, Shunpei Yamazaki
2014	B	`conf`	Improving polynomial datapath debugging with HEDs. ETS Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
2014	C	`conf`	Logic synthesis and verification on fixed topology. VLSI-SoC Masahiro Fujita, Alan Mishchenko
2014	A	`conf`	MAESTRO: A time-driven embedded testbed Architecture with Event-driven Synchronization. RTAS Sriram Karunagaran, Karuna P. Sahoo, Jayaraj Poroor, Masahiro Fujita
2014	—	`conf`	Multi-step image compositing for massively parallel rendering. HPCS Jorji Nonaka, Kenji Ono, Masahiro Fujita
2014	—	`conf`	RTL datapath optimization using system-level transformations. ISQED Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
2014	J	`jnl`	SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. IPSJ Trans. Syst. LSI Des. Methodol. Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita
2014	—	`conf`	Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults. ISVLSI Masahiro Fujita
2014	C	`conf`	i/k-Contact: A context-aware user authentication using physical social trust. PST Shiori Arimura, Masahiro Fujita, Shinya Kobayashi, Junya Kani, Masakatsu Nishigaki, Akira Shiba
2013	C	`conf`	A debugging method for gate level circuit designs by introducing programmability. VLSI-SoC Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita
2013	—	`conf`	Debugging Methods Through Identification of Appropriate Functions for Internal Gates. VLSI-SoC (Selected Papers) Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita
2013	C	`conf`	FOF: Functionally Observable Fault and its ATPG techniques. VLSI-SoC Masahiro Fujita, Takeshi Matsumoto, Satoshi Jo
2013	A	`conf`	Hardware implementation of BLTL property checkers for acceleration of statistical model checking. ICCAD Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita
2013	A	`conf`	Partial synthesis through sampling with and without specification. ICCAD Masahiro Fujita, Satoshi Jo, Shohei Ono, Takeshi Matsumoto
2013	Misc	`conf`	Special session 4B: Elevator talks. VTS Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia
2013	Misc	`conf`	Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. VLSI Design Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal
2012	—	`conf`	A functional test generation technique for RTL datapaths. HLDVT Bijan Alizadeh, Masahiro Fujita
2012	C	`conf`	An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence. VLSI-SoC Takeshi Matsumoto, Shohei Ono, Masahiro Fujita
2012	—	`conf`	Automated data analysis techniques for a modern silicon debug environment. ASP-DAC Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita
2012	C	`conf`	Automatic assertion extraction in gate-level simulation using GPGPUs. ICCD Shohei Ono, Takeshi Matsumoto, Masahiro Fujita
2012	—	`conf`	Distance aware ray tracing for curves. SIGGRAPH Posters Koji Nakamaru, Toru Matsuoka, Masahiro Fujita
2012	A*	`conf`	Future direction of digital content: 20th anniversary keynote talk. ACM Multimedia Masahiro Fujita
2012	—	`conf`	On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita
2012	C	`conf`	Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2 MEMOCODE Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita
2012	A	`conf`	Post-silicon debugging targeting electrical errors with patchable controllers (abstract only). FPGA Masahiro Fujita, Hiroaki Yoshida
2012	—	`conf`	Post-silicon patching for verification/debugging with high-level models and programmable logic. ASP-DAC Masahiro Fujita, Hiroaki Yoshida
2012	—	`conf`	Post-silicon verification and debugging with control flow traces and patchable hardware. HLDVT Masahiro Fujita
2012	—	`conf`	SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. Asian Test Symposium Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita
2012	—	`conf`	SEU Tolerant Robust Latch Design. VDAT Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita
2012	C	`conf`	SEU tolerant robust memory cell design. IOLTS Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita
2012	C	`conf`	Simulation-Based Analysis of Cyberphysical Systems. DSD Masahiro Fujita
2012	J	`jnl`	Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports Görschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik Roy, Matteo Sonza Reorda
2011	—	`conf`	Accelerating Tsunami simulation with FPGA and GPU through automatic compilation. ACWR Masahiro Fujita
2011	J	`jnl`	An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita
2011	Misc	`conf`	An energy-efficient patchable accelerator for post-silicon engineering changes. CODES+ISSS Hiroaki Yoshida, Masahiro Fujita
2011	—	`conf`	Automated System Testing of Dynamic Web Applications. ICSOFT (Selected Papers) Hideo Tanida, Mukul R. Prasad, Sreeranga P. Rajan, Masahiro Fujita
2011	—	`conf`	Client-tier Validation of Dynamic Web Applications. ICSOFT (2) Hideo Tanida, Masahiro Fujita, Mukul R. Prasad, Sreeranga P. Rajan
2011	J	`jnl`	Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture. IPSJ Trans. Syst. LSI Des. Methodol. Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan, Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani Narayan
2011	—	`conf`	Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. ARC Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan
2011	—	`conf`	Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques. ISQED Bijan Alizadeh, Masahiro Fujita
2011	C	`conf`	Early case splitting and false path detection to improve high level ATPG techniques. ISCAS Bijan Alizadeh, Masahiro Fujita
2011	J	`jnl`	Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability. Inf. Media Technol. Hiroaki Yoshida, Masahiro Fujita
2011	J	`jnl`	Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability. IPSJ Trans. Syst. LSI Des. Methodol. Hiroaki Yoshida, Masahiro Fujita
2011	—	`conf`	High Level Verification and Its Use at Pos-Silicon Debugging and Patching. Asian Test Symposium Masahiro Fujita
2011	—	`conf`	Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture. FPT Ratna Krishnamoorthy, Masahiro Fujita, Keshavan Varadarajan, S. K. Nandy
2011	—	`conf`	Modular equivalence verification of polynomial datapaths with multiple word-length operands. HLDVT Bijan Alizadeh, Masahiro Fujita
2011	J	`jnl`	Multi-Level Bounded Model Checking with Symbolic Counterexamples. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita
2011	—	`conf`	On-chip dynamic signal sequence slicing for efficient post-silicon debugging. ASP-DAC Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita
2011	J	`jnl`	Performance-Constrained Transistor Sizing for Different Cell Count Minimization. Inf. Media Technol. Hiroaki Yoshida, Masahiro Fujita
2011	—	`conf`	SEU tolerant SRAM cell. ISQED Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita
2011	B	`conf`	Synthesizing, Verifying, and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols. ATVA Masahiro Fujita
2011	—	`conf`	Tutorial: "Post silicon debug of SOC designs". SoCC Virendra Singh, Masahiro Fujita
2011	—	`conf`	Utilizing high level design information to speed up post-silicon debugging. ASP-DAC Masahiro Fujita
2010	—	`conf`	A debugging method for repairing post-silicon bugs of high performance processors in the fields. FPT Bijan Alizadeh, Masahiro Fujita
2010	J	`jnl`	Changes of brain phosphodiesterase 4 in major depression. NeuroImage Masahiro Fujita, Alan G. Mallinger, Carlos A. Zarate Jr., Leah P. Dickstein, Sami S. Zoghbi, Victor W. Pike, Yi Zhang, Robert B. Innis, Wayne C. Drevets
2010	J	`jnl`	Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bijan Alizadeh, Mohammad Mirzaei, Masahiro Fujita
2010	J	`jnl`	Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. Inf. Media Technol. Kenshu Seto, Masahiro Fujita
2010	J	`jnl`	Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. IPSJ Trans. Syst. LSI Des. Methodol. Kenshu Seto, Masahiro Fujita
2010	—	`conf`	DNA-grafted-polymer mediated self-assembly of micro components. NEMS Guillermo Lopez, Tomoki Tanemura, Ryo Sato, Takahiro Saeki, Yoshikazu Hirai, Koji Sugano, Toshiyuki Tsuchiya, Osamu Tabata, Masahiro Fujita, Mizuo Maeda
2010	C	`conf`	Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging. ICCD Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita
2010	—	`conf`	Guided gate-level ATPG for sequential circuits using a high-level test generation approach. ASP-DAC Bijan Alizadeh, Masahiro Fujita
2010	J	`jnl`	Modular Datapath Optimization and Verification Based on Modular-HED. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bijan Alizadeh, Masahiro Fujita
2010	J	`jnl`	Performance Estimation with Automatic False-Path Detection for System-Level Designs. IPSJ Trans. Syst. LSI Des. Methodol. Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita
2010	J	`jnl`	Performance-Constrained Transistor Sizing for Different Cell Count Minimization. J. Inf. Process. Hiroaki Yoshida, Masahiro Fujita
2010	A	`conf`	Polynomial datapath optimization using constraint solving and formal modelling. ICCAD Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler
2010	—	`conf`	SEU tolerant SRAM for FPGA applications. FPT Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita
2010	—	`conf`	Synthesis and formal verification of on-chip protocol transducers through decomposed specification. ISQED Masahiro Fujita, Hideo Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto
2010	Misc	`conf`	Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. CASES Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita
2009	—	`conf`	09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers. Algorithms and Applications for Next Generation SAT Solvers Bernd Becker, Valeria Bertacco, Rolf Drechsler, Masahiro Fujita
2009	J	`jnl`	A Formal Approach for Debugging Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Omid Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita
2009	—	`conf`	A Post-Silicon Debug Support Using High-Level Design Description. Asian Test Symposium Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita
2009	J	`jnl`	A Unified Framework for Equivalence Verification of Datapath Oriented Applications. IEICE Trans. Inf. Syst. Bijan Alizadeh, Masahiro Fujita
2009	—	`ed.`	Algorithms and Applications for Next Generation SAT Solvers, 08.11. - 13.11.2009 Algorithms and Applications for Next Generation SAT Solvers Bernd Becker, V. Bertacoo, Rolf Drechsler, Masahiro Fujita
2009	J	`jnl`	Functional Equivalence Verification Tools in High-Level Synthesis Flows. IEEE Des. Test Comput. Anmol Mathur, Masahiro Fujita, Edmund M. Clarke, Pascal Urard
2009	C	`conf`	High-level optimization of integer multipliers over a finite bit-width with verification capabilities. MEMOCODE Omid Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita
2009	A	`conf`	Improved heuristics for finite word-length polynomial datapath optimization. ICCAD Bijan Alizadeh, Masahiro Fujita
2009	—	`conf`	Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences. ISQED Hiroaki Yoshida, Masahiro Fujita
2009	J	`jnl`	Intelligence Dynamics: a concept and preliminary experiments for open-ended learning agents. Auton. Agents Multi Agent Syst. Masahiro Fujita
2009	J	`jnl`	Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
2009	—	`conf`	Modular arithmetic decision procedure with auto-correction mechanism. HLDVT Bijan Alizadeh, Masahiro Fujita
2009	A*	`conf`	Polynomial datapath optimization using partitioning and compensation heuristics. DAC Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita
2009	J	`jnl`	Trends in Formal Verification Techniques for C-based Hardware Designs. Inf. Media Technol. Masahiro Fujita
2009	J	`jnl`	Trends in Formal Verification Techniques for C-based Hardware Designs. IPSJ Trans. Syst. LSI Des. Methodol. Masahiro Fujita
2009	J	`jnl`	Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath. IEICE Trans. Inf. Syst. Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita
2008	J	`jnl`	3D Perception and Environment Map Generation for Humanoid Robot Navigation. Int. J. Robotics Res. Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita
2008	—	`conf`	A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams. ICSOFT (SE/MUSE/GSDCA) Masahiro Fujita, Takeshi Matsumoto, Hiroaki Yoshida
2008	A*	`conf`	Adaptive grasping by multi fingered hand with tactile sensor based on robust force and position control. ICRA Taro Takahashi, Toshimitsu Tsuboi, Takeo Kishida, Yasunori Kawanami, Satoru Shimizu, Masatsugu Iribe, Tetsuharu Fukushima, Masahiro Fujita
2008	—	`conf`	An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs. ATS Yoshihisa Kojima, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita
2008	C	`conf`	Arithmetic Circuits Verification without Looking for Internal Equivalences. MEMOCODE Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita
2008	—	`conf`	Custom Instruction Generation with High-Level Synthesis. SASP Kenshu Seto, Masahiro Fujita
2008	J	`jnl`	Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation. J. Satisf. Boolean Model. Comput. Masahiro Fujita, Kenshu Seto, Thanyapat Sakunkonchak
2008	A	`conf`	Motion control of a virtual humanoid that can perform real physical interactions with a human. IROS Ken'ichiro Nagasaka, Atsushi Miyamoto, Masakuni Nagano, Hirokazu Shirado, Tetsuharu Fukushima, Masahiro Fujita
2008	—	`conf`	Multi-level Bounded Model Checking to detect bugs beyond the bound. HLDVT Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita
2008	A	`conf`	Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits. DATE Hiroaki Yoshida, Masahiro Fujita
2008	C	`conf`	Rule-Based Approaches for Equivalence Checking of SpecC Programs. MEMOCODE Subash Shankar, Masahiro Fujita
2008	Misc	`conf`	Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram. CSICC Bijan Alizadeh, Masahiro Fujita
2008	—	`conf`	Targeting Leakage Constraints during ATPG. ATS Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
2008	—	`book`	Verification Techniques for System-Level Design. Masahiro Fujita, Indradeep Ghosh, Mukul R. Prasad
2007	—	`conf`	A novel formal approach to generate high-level test vectors without ILP and SAT solvers. HLDVT Bijan Alizadeh, Masahiro Fujita
2007	B	`conf`	Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. ATVA Bijan Alizadeh, Masahiro Fujita
2007	—	`conf`	Development and Verification of a Collaborative Printing Environment. C5 Takeshi Matsumoto, Daisuke Ando, Tasuku Nishihara, Masahiro Fujita
2007	J	`jnl`	Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph. J. Univers. Comput. Sci. Shunsuke Sasaki, Tasuku Nishihara, Daisuke Ando, Masahiro Fujita
2007	—	`conf`	Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. IESS Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
2007	—	`conf`	Lateral State Prediction for Automated Steering using Reliability-Weighted Measurements from Multiple Sensors. ITSC Makoto Aso, Masahiro Fujita, Keitaro Niki
2007	J	`jnl`	Multiscale simulation method for self-organization of nanoparticles in dense suspension. J. Comput. Phys. Masahiro Fujita, Yukio Yamaguchi
2007	—	`conf`	Protocol Transducer Synthesis using Divide and Conquer approach. ASP-DAC Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita
2007	B	`conf`	Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction. ATVA Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
2007	—	`conf`	VLSI CAD Education and Exercise Course with Public Domain Tools. MSE Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada
2006	C	`conf`	An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme. ISCAS Satoshi Komatsu, Masahiro Fujita
2006	—	`conf`	Dynamically reconfigurable protocol transducer. FPT Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
2006	J	`jnl`	Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions. Int. J. Parallel Program. David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, Sreeranga P. Rajan
2006	—	`conf`	Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs. ISQED Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita
2006	—	`conf`	Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis. HLDVT Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita
2006	C	`conf`	Equivalence checking: a rule-based approach. MEMOCODE Masahiro Fujita, Subash Shankar, Sasaki Shunsuke
2006	—	`conf`	Object-oriented analysis and specification for HW/SW co-design with UML diagrams. ACST Ken Matsui, Masahiro Fujita
2006	Misc	`conf`	Sequential Equivalence Checking. VLSI Design Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra
2006	J	`jnl`	Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yu Liu, Satoshi Komatsu, Masahiro Fujita
2006	J	`jnl`	Synchronization Verification in System-Level Design with ILP Solvers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
2006	—	`conf`	System LSI distributed collaborative design environment for both designers and CAD developers/engineers. C5 Masahiro Fujita, Tasuku Nishihara, Daisuke Ando
2006	J	`jnl`	The AMS Extension to System Level Design Language - SpecC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yu Liu, Satoshi Komatsu, Masahiro Fujita
2005	A*	`conf`	A Floor and Obstacle Height Map for 3D Navigation of a Humanoid Robot. ICRA Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita
2005	—	`conf`	A modular architecture for humanoid robot navigation. Humanoids Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita
2005	C	`conf`	AMS Extensions for Timed/Untimed System-Level Design Language. FDL Yu Liu, Satoshi Komatsu, Masahiro Fujita
2005	J	`jnl`	An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita
2005	J	`jnl`	Autonomous evolution of dynamic gaits with two quadruped robots. IEEE Trans. Robotics Gregory S. Hornby, Seiichi Takamura, Takashi Yamamoto, Masahiro Fujita
2005	—	`conf`	Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths. CHARME Masahiro Fujita
2005	J	`jnl`	Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths. ACM Trans. Design Autom. Electr. Syst. Masahiro Fujita
2005	C	`conf`	Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTL. MEMOCODE Masahiro Fujita
2005	—	`conf`	Hexagonal storage scheme for interleaved frame buffers and textures. Graphics Hardware Yosuke Bando, Takahiro Saito, Masahiro Fujita
2005	J	`jnl`	Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Satoshi Komatsu, Masahiro Fujita
2005	Misc	`conf`	Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse. IRI Masahiro Fujita, Shunsuke Sasaki, Ken Matsui
2005	—	`conf`	Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. FPT Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
2005	A*	`conf`	Real-Time Path Planning for Humanoid Robot Navigation. IJCAI Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita
2005	—	`conf`	Slicing-based Hardware/Software Co-design Methodology From Functional Specifications. FSEN Shunsuke Sasaki, Tasuku Nishihara, Masahiro Fujita
2005	C	`conf`	Synchronization verification in system-level design with ILP solvers. MEMOCODE Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
2005	—	`conf`	System level design language extensions for timed/untimed digital-analog combined system design. ACM Great Lakes Symposium on VLSI Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
2004	C	`conf`	Associated Emotion and Its Expression in an Entertainment Robot QRIO. ICEC Fumihide Tanaka, Kuniaki Noda, Tsutomu Sawada, Masahiro Fujita
2004	A*	`conf`	Behavior Description and Control using Behavior Module for Personal Robot. ICRA Yukiko Hoshino, Tsuyoshi Takagi, Ugo Di Profio, Masahiro Fujita
2004	A	`conf`	Behavior selection and motion modulation in emotionally grounded architecture for QRIO SDR-4XII. IROS Tsutomu Sawada, Tsuyoshi Takagi, Masahiro Fujita
2004	Misc	`conf`	Formal Verification of C Language Based VLSI Designs. VLSI Design Masahiro Fujita
2004	Misc	`conf`	High Level Design Validation: Current Practices and Future Directions. VLSI Design Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita
2004	—	`conf`	Learning behavior selection through interaction based on emotionally grounded symbol concept. Humanoids Tsutomu Sawada, Tsuyoshi Takagi, Yukiko Hoshino, Masahiro Fujita
2004	J	`jnl`	On activating human communications with pet-type robot AIBO. Proc. IEEE Masahiro Fujita
2004	—	`conf`	On equivalence checking between behavioral and RTL descriptions. HLDVT Masahiro Fujita
2004	—	`conf`	Precomputed Radiance Transfer with Spatially-Varying Lighting Effects. CGIV Masahiro Fujita, Takashi Kanai
2004	A	`conf`	Stair climbing for humanoid robots using stereo vision. IROS Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita
2003	A*	`conf`	A small biped entertainment robot exploring attractive applications. ICRA Yoshihiro Kuroki, Masahiro Fujita, Tatsuzo Ishida, Ken'ichiro Nagasaka, Jin'ichi Yamaguchi
2003	J	`jnl`	An Overview of RoboCup-2002 Fukuoka/Busan. AI Mag. Minoru Asada, Oliver Obst, Daniel Polani, Brett Browning, Andrea Bonarini, Masahiro Fujita, Thomas Christaller, Tomoichi Takahashi, Satoshi Tadokoro, Elizabeth Sklar, Gal A. Kaminka
2003	J	`jnl`	An ethological and emotional basis for human-robot interaction. Robotics Auton. Syst. Ronald C. Arkin, Masahiro Fujita, Tsuyoshi Takagi, Rika Hasegawa
2003	A	`conf`	Autonomous behavior control architecture of entertainment humanoid robot SDR-4X. IROS Masahiro Fujita, Yoshihiro Kuroki, Tatsuzo Ishida, Toshi T. Doi
2003	—	`conf`	Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada
2003	C	`conf`	Engineering Changes in Field Modifiable Architectures. MEMOCODE Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita
2003	—	`conf`	Event-driven observability enhanced coverage analysis of C programs for functional validation. ASP-DAC Farzan Fallah, Indradeep Ghosh, Masahiro Fujita
2003	—	`conf`	Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. HICSS Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima
2003	A*	`conf`	Formal verification - prove it or pitch it. DAC Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi
2003	A*	`conf`	High Presence Remote Presentation in the Shared Immersive Virtual World. VR Tetsuro Ogi, Toshio Yamada, Michitaka Hirose, Masahiro Fujita, Kazuto Kuzuu
2003	J	`jnl`	Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Satoshi Komatsu, Masahiro Fujita
2003	—	`conf`	Irredundant address bus encoding techniques based on adaptive codebooks for low power. ASP-DAC Satoshi Komatsu, Masahiro Fujita
2003	—	`conf`	Logic optimization for asynchronous speed independent controllers using transduction method. ASP-DAC Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya
2003	A	`conf`	Model Checking for Dependable Software-Intensive Systems. DSN Edmund M. Clarke, Masahiro Fujita, David P. Gluch
2003	C	`conf`	SDR-4X II: A Small Humanoid as an Entertainer in Home Environment. ISRR Masahiro Fujita, Kohtaro Sabe, Yoshihiro Kuroki, Tatsuzo Ishida, Toshi T. Doi
2003	J	`jnl`	Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
2002	J	`jnl`	A Small Biped Entertainment Robot. J. Robotics Mechatronics Yoshihiro Kuroki, Tatsuzo Ishida, Jin'ichi Yamaguchi, Masahiro Fujita, Toshi T. Doi
2002	—	`conf`	An equivalence checking methodology for hardware oriented C-based specifications. HLDVT Hiroshi Saito, Takaya Ogawa, Thanyapat Sakunkonchak, Masahiro Fujita, Takashi Nanya
2002	—	`conf`	Debug methodology for arithmetic circuits on FPGAs. FPT Masao Kubo, Masahiro Fujita
2002	J	`jnl`	Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods Syst. Des. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita
2002	—	`conf`	Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. IWLS Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
2002	—	`conf`	Field modifiable architecture with FPGAs and its design methodology. FPT Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita
2002	C	`conf`	Formal Verification of a Pipelined Processor with New Memory. PRDC Hiroshi Nakamura, Takanori Arai, Masahiro Fujita
2002	—	`conf`	Hardware-Assisted Relief Texture Mapping. Eurographics (Short Presentations) Masahiro Fujita, Takashi Kanai
2002	—	`conf`	Logic Optimization for Asynchronous SI Controllers using Transduction Method. IWLS Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya
2002	J	`jnl`	Program slicing for VHDL. Int. J. Softw. Tools Technol. Transf. Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum
2002	—	`conf`	Simultaneous Circuit Transformation and Routing. ASP-DAC/VLSI Design Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita
2002	C	`conf`	Sony Four Legged Robot League at RoboCup 2002. RoboCup Masahiro Fujita
2002	C	`conf`	Verification of Event-Based Synchronization of SpecC Description Using Difference Decision Diagrams. FORTE Thanyapat Sakunkonchak, Masahiro Fujita
2001	J	`jnl`	A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. IEEE Trans. Computers Jawahar Jain, Ingo Wegener, Masahiro Fujita
2001	J	`jnl`	AIBO: Toward the Era of Digital Creatures. Int. J. Robotics Res. Masahiro Fujita
2001	—	`conf`	Architecture and preliminary experimental results for emotionally grounded symbol acquisition. Agents Masahiro Fujita, Gabriel Costa, Rika Hasegawa, Tsuyoshi Takagi, Jun Yokono, Hideki Shimomura
2001	J	`jnl`	Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Indradeep Ghosh, Masahiro Fujita
2001	A*	`conf`	Ethological Modeling and Architecture for an Entertainment Robot. ICRA Ronald C. Arkin, Masahiro Fujita, Tsuyoshi Takagi, Rika Hasegawa
2001	A	`conf`	Motion entertainment by a small humanoid robot based on OPEN-R. IROS Tatsuzo Ishida, Yoshihiro Kuroki, Jin'ichi Yamaguchi, Masahiro Fujita, Toshi T. Doi
2001	Misc	`conf`	Multiresolution Interpolation Meshes. PG Takashi Michikawa, Takashi Kanai, Masahiro Fujita, Hiroaki Chiyokura
2001	—	`conf`	New Design Paradigms: What Needs to be Standardized?. ISSS Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda
2001	—	`conf`	The standard SpecC language. ISSS Masahiro Fujita, Hiroshi Nakamura
2000	A	`conf`	A quadruped robot platform with basic software for RoboCup-99 legged robot league. IROS Takashi Yamamoto, Masahiro Fujita
2000	—	`conf`	Automatic partitioning for efficient combinatorial verification. ASP-DAC Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita
2000	A*	`conf`	Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. DAC Indradeep Ghosh, Masahiro Fujita
2000	A*	`conf`	Digital Creatures for Future Entertainment Robotics. ICRA Masahiro Fujita
2000	A*	`conf`	Efficient variable ordering using aBDD based sampling. DAC Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita
2000	—	`conf`	Evolution of Controllers from a High-Level Simulator to a High DOF Robot. ICES Gregory Hornby, Seiichi Takamura, Osamu Hanagata, Masahiro Fujita, Jordan B. Pollack
2000	A*	`conf`	Evolving Robust Gaits with AIBO. ICRA Gregory Hornby, Seiichi Takamura, Jun Yokono, Osamu Hanagata, Takashi Yamamoto, Masahiro Fujita
2000	Misc	`conf`	Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
2000	Misc	`conf`	Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao
1999	J	`jnl`	A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library. Des. Autom. Embed. Syst. Ashok Sudarsanam, Sharad Malik, Masahiro Fujita
1999	A	`conf`	An Efficient Filter-Based Approach for Combinational Verification. DATE Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
1999	J	`jnl`	An efficient filter-based approach for combinational verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
1999	—	`conf`	Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. CODES Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik
1999	Misc	`conf`	Efficient Scheduling Techniques for ROBDD Construction. VLSI Design Rajeev Murgai, Jawahar Jain, Masahiro Fujita
1999	A*	`conf`	Model Checking Based on Sequential ATPG. CAV Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita
1999	A*	`conf`	Multiple Error Diagnosis Based on Xlists. DAC Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni
1999	A	`conf`	On Reducing Transitions Through Data Modifications. DATE Rajeev Murgai, Masahiro Fujita
1999	Misc	`conf`	On the Evaluation of Arbitrary Defect Coverage of Test Sets. VTS Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita
1999	—	`conf`	Program Slicing of Hardware Description Languages. CHARME Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum
1999	—	`conf`	Speeding Up Look-up-Table Driven Logic Simulation. VLSI Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita
1999	A*	`conf`	Symbolic Model Checking Using SAT Procedures instead of BDDs. DAC Armin Biere, Alessandro Cimatti, Edmund M. Clarke, Masahiro Fujita, Yunshan Zhu
1998	J	`jnl`	ATM switch design by high-level modeling, formal verification and high-level synthesis. ACM Trans. Design Autom. Electr. Syst. Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee
1998	Misc	`conf`	Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. VLSI Design Sreeranga P. Rajan, Masahiro Fujita
1998	—	`conf`	Model Checking: Its Basics and Reality (Embedded Tutorial). ASP-DAC Masahiro Fujita
1998	A	`conf`	Modeling the unknown! Towards model-independent fault and error diagnosis. ITC Vamsi Boppana, Masahiro Fujita
1998	A	`conf`	Sampling schemes for computing OBDD variable orderings. ICCAD Jawahar Jain, William Adams, Masahiro Fujita
1998	—	`conf`	Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol. FM-Trends Masahiro Fujita, Sreeranga P. Rajan, Alan J. Hu
1998	A*	`conf`	Using Complementation and Resequencing to Minimize Transitions. DAC Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira
1997	C	`conf`	A Survey of Techniques for Formal Verification of Combinational Circuits. ICCD Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
1997	A	`conf`	A proposal of a quadruped robot platform for RoboCup. IROS Masahiro Fujita, Koji Kageyama
1997	—	`conf`	ATM Switch Design: Parametric High-Level Modeling and Formal Verification. AMAST Sreeranga P. Rajan, Masahiro Fujita
1997	—	`conf`	An Open Architecture for Robot Entertainment. Agents Masahiro Fujita, Koji Kageyama
1997	J	`jnl`	Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping. Des. Autom. Embed. Syst. Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
1997	Misc	`conf`	Formal Verification of Combinational Circuit. VLSI Design Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
1997	C	`conf`	Formal Verification of the HAL S1 System Cache Coherence Protocol. ICCD Alan J. Hu, Masahiro Fujita, Chris Wilson
1997	J	`jnl`	Introduction to the Special Issue on Multi-Terminal Binary Decision Diagrams. Formal Methods Syst. Des. Masahiro Fujita, Patrick C. McGeer
1997	J	`jnl`	Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation. Formal Methods Syst. Des. Masahiro Fujita, Patrick C. McGeer, Jerry Chih-Yuan Yang
1997	J	`jnl`	Power analysis and minimization techniques for embedded DSP software. IEEE Trans. Very Large Scale Integr. Syst. Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
1997	Misc	`conf`	Some Recent Advances in Software and Hardware Logic Simulation. VLSI Design Rajeev Murgai, Masahiro Fujita
1997	J	`jnl`	Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. Formal Methods Syst. Des. Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, Jerry Chih-Yuan Yang
1997	A	`conf`	Speeding up technology-independent timing optimization by network partitioning. ICCAD Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita
1996	Misc	`conf`	A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	B	`conf`	Decomposition Techniques for Efficient ROBDD Construction. FMCAD Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
1996	A*	`conf`	Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. DAC Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
1996	J	`jnl`	Hybrid Position and Force Control Without Force Sensor. J. Robotics Mechatronics Kiyoshi Ohishi, Masaru Miyazaki, Masahiro Fujita
1996	Misc	`conf`	On More Efficient Combinational ATPG Using Functional Learning. VLSI Design Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
1996	A	`conf`	Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. ICCAD Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
1996	A*	`conf`	Verification of Arithmetic Circuits by Comparing Two Similar Circuits. CAV Masahiro Fujita
1995	A*	`conf`	Advanced Verification Techniques Based on Learning. DAC Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita
1995	A	`conf`	Hybrid decision diagrams. ICCAD Edmund M. Clarke, Masahiro Fujita, Xudong Zhao
1995	C	`conf`	Logic synthesis for a single large look-up table. ICCD Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose
1995	—	`conf`	Power analysis and low-power scheduling techniques for embedded DSP software. ISSS Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
1995	—	`conf`	VERIFUL: VERIfication using FUnctional Learning. ED&TC Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
1994	A	`conf`	A redesign technique for combinational circuits based on gate reconnections. ICCAD Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton
1994	—	`conf`	Bug Identification of a Real Chip Design by Symbolic Model Checking. EDAC-ETC-EUROASIC Ben Chen, Michihiro Yamazaki, Masahiro Fujita
1994	C	`conf`	Fast Spectrum Computation for Logic Functions using Binary Decision Diagrams. ISCAS Masahiro Fujita, Jerry Chih-Yuan Yang, Edmund M. Clarke, Xudong Zhao, Patrick C. McGeer
1994	A	`conf`	LP based cell selection with constraints of timing, area, and power consumption. ICCAD Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita
1994	C	`conf`	YEPHCAD and FLORA: Logic Synthesis for Control and Datapath. ICCD Hitomi Sato, Michihiro Yamazaki, Masahiro Fujita
1993	—	`conf`	Motion Planning and Control for a Robot Performer. ICRA (3) Takeshi Sakaguchi, Masahiro Fujita, Hiroshi Watanabe, Fumio Miyazaki
1993	A*	`conf`	Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. DAC Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, Jerry Chih-Yuan Yang
1993	C	`conf`	Synthesis of Controllers from Interval Temporal Logic Specification. ICCD Masahiro Fujita, Shinji Kono
1993	J	`jnl`	Variable ordering algorithms for ordered binary decision diagrams and their evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga
1992	A*	`conf`	Efficient Sum-to-One Subsets Algorithm for Logic Optimization. DAC Kuang-Chien Chen, Masahiro Fujita
1992	A*	`conf`	Force control without force sensor based on mixed sensitivity H ICRA Kiyoshi Ohishi, Masaru Miyazaki, Masahiro Fujita, Yasumasa Ogino
1992	B	`conf`	Patching Method for Lookup-Table Type FPLs. FPL Masahiro Fujita, Yuji Kukimoto
1992	C	`conf`	RTL Design Verification by Making Use of Datapath Information. ICCD Masahiro Fujita
1992	A	`conf`	Rectification method for lookup-table type FPGA's. ICCAD Yuji Kukimoto, Masahiro Fujita
1991	A*	`conf`	A Resynthesis Approach for Network Optimization. DAC Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
1991	—	`conf`	Analysis of Neighborhood Interaction in Kohonen Neural Networks. IPPS Zhen-Ping Lo, Masahiro Fujita, Behnam Bavarian
1991	A	`conf`	Application of Boolean Unification to Combinational Logic Synthesis. ICCAD Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen
1991	C	`conf`	Concurrent Resynthesis for Network Optimization. ICCD Kuang-Chien Chen, Masahiro Fujita
1991	A	`conf`	Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. ICCAD Masahiro Fujita, Yusuke Matsunaga
1991	—	`conf`	On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. EURO-DAC Masahiro Fujita, Yusuke Matsunaga, Taeko Kakuda
1990	A*	`conf`	A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. CAV Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka
1990	—	`conf`	A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. CAV (DIMACS/AMS volume) Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka
1990	A	`conf`	Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. ICCAD Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda
1990	A*	`conf`	Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. DAC Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita
1990	C	`conf`	Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams. ICCD Hitomi Sato, Norikazu Takahashi, Yusuke Matsunaga, Masahiro Fujita
1990	—	`conf`	Implementation of ANN on RISC processor array. ASAP Atsunobu Hiraiwa, Masahiro Fujita, Shigeru Kurosu, Shigeru Arisawa, Makoto Inoue
1990	A	`conf`	Multi-Level Logic Minimization Across Latch Boundaries. ICCAD Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda
1990	C	`conf`	Practical design assistance at register transfer level using a data path verifier. ICCD Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka
1990	J	`jnl`	Speed tunable finite state machine compiler: Zephcad. Microprocess. Microsystems Hitomi Sato, Yoshihide Sugiura, Masahiro Fujita
1989	—	`conf`	Logic Design Assistence Using Temporal Logic Based Language Tokio. LP Hiroshi Nakamura, Masaya Nakai, Shinji Kono, Masahiro Fujita, Hidehiko Tanaka
1989	A	`conf`	Multi-level logic optimization using binary decision diagrams. ICCAD Yusuke Matsunaga, Masahiro Fujita
1988	A	`conf`	Evaluation and improvement of Boolean comparison method based on binary decision diagrams. ICCAD Masahiro Fujita, Hisanori Fujisawa, Nobuaki Kawato
1986	B	`conf`	Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog. ICLP Masahiro Fujita, Shinji Kono, Hidehiko Tanaka, Tohru Moto-Oka
1985	—	`conf`	Implementation of Temporal Logic Programming Language Tokio. LP Shinji Kono, T. Aoyagi, Masahiro Fujita, Hidehiko Tanaka
1985	—	`conf`	Temporal Logic Programming Language Tokio - Programming in Tokio. LP T. Aoyagi, Masahiro Fujita, Tohru Moto-Oka
1985	—	`conf`	Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis. LP Masahiro Fujita, Makoto Ishisone, Hiroshi Nakamura, Hidehiko Tanaka, Tohru Moto-Oka
1984	—	`conf`	Specifying Hardware in temporal Logic & Efficient Synthesis of State-Diagrams Using Prolog. FGCS Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka
1983	J	`jnl`	Temporal Logic Based Hardware Description and Its Verification with Prolog. New Gener. Comput. Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka