Masahiro Aoyagi

36 papers Misc 1Journal 11Unranked 24

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System. COOL CHIPS Takeshi Ohkawa, Masahiro Aoyagi
2019	—	`conf`	Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs. 3DIC Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi
2019	—	`conf`	Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. 3DIC Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
2017	—	`conf`	Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus. MCSoC Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Katsuya Kikuchi, Masahiro Aoyagi
2017	J	`jnl`	Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
2016	—	`conf`	3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions. 3DIC Makoto Motoyoshi, Kohki Yanagimura, Taikoh Fushimi, Junichi Takanohashi, Mariappan Murugesan, Masahiro Aoyagi, Mitsumasa Koyanagi
2016	J	`jnl`	Fabrication and stress analysis of annular-trench-isolated TSV. Microelectron. Reliab. Wei Feng, Tung Thanh Bui, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
2016	J	`jnl`	Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
2016	—	`conf`	Two-axis tilt angle detection based on dielectric liquid capacitive sensor. IEEE SENSORS Tiep Dang Dinh, Tung Thanh Bui, Tuan Vu Quoc, Thinh Pham Quoc, Masahiro Aoyagi, My Bui Ngoc, Trinh Chu Duc
2016	J	`jnl`	Validation of TSV thermo-mechanical simulation by stress measurement. Microelectron. Reliab. Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
2016	—	`conf`	Wet cleaning process for high-yield via-last TSV formation. 3DIC Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura
2015	—	`conf`	Guard-ring monitoring system for inspecting defects in TSV-based data buses. 3DIC Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi
2015	J	`jnl`	Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit. Microelectron. J. Samson Melamed, Fumito Imura, Hiroshi Nakagawa, Katsuya Kikuchi, Michiya Hagimoto, Yukoh Matsumoto, Masahiro Aoyagi
2015	—	`conf`	Investigation of effects of metalization on heat spreading in bump-bonded 3D systems. 3DIC Samson Melamed, Katsuya Kikuchi, Masahiro Aoyagi
2015	—	`conf`	Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner. 3DIC Tung Thanh Bui, Naoya Watanabe, Masahiro Aoyagi, Katsuya Kikuchi
2014	—	`conf`	Analysis of thermal stress distribution for TSV with novel structure. 3DIC Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
2014	—	`conf`	Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. 3DIC Bui Thanh Tung, Xiaojin Cheng, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, Masahiro Aoyagi
2014	—	`conf`	Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal. 3DIC Naoya Watanabe, Masahiro Aoyagi, Daisuke Katagawa, Tsubasa Bandoh, Takahiko Mitsui, Eiichi Yamamoto
2014	—	`conf`	Substrate monitoring system for inspecting defects in TSV-based data buses. 3DIC Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi
2014	—	`conf`	Ultrawideband ultralow PDN impedance of decoupling capacitor embedded interposers using narrow gap chip parts mounting technology for 3-D integrated LSI system. 3DIC Katsuya Kikuchi, Masahiro Aoyagi, Masaaki Ujiie, Shinya Takayama
2013	—	`conf`	Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging. 3DIC Katsuya Kikuchi, Fumiki Kato, Shunsuke Nemoto, Hiroshi Nakagawa, Masahiro Aoyagi, Youtaro Yasu, Kohji Koshiji
2013	—	`conf`	New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. 3DIC Masahiro Aoyagi, Naoya Watanabe, Motohiro Suzuki, Katsuya Kikuchi, Shunsuke Nemoto, Noriaki Arima, Misaki Ishizuka, Koji Suzuki, Toshio Shiomi
2013	Misc	`conf`	Special session 4C: Hot topic 3D-IC design and test. VTS Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai
2012	—	`conf`	Cool System scalable 3-D stacked heterogeneous Multi-Core / Multi-Chip architecture for ultra low-power digital TV applications. COOL Chips Yukoh Matsumoto, Tomoyuki Morimoto, Michiya Hagimoto, Hiroyuki Uchida, Nobuyuki Hikichi, Fumito Imura, Hiroshi Nakagawa, Masahiro Aoyagi
2011	—	`conf`	COOL interconnect low power interconnection technology for scalable 3D LSI design. COOL Chips Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto, Fumito Imura, Motohiro Suzuki, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi
2011	—	`conf`	Damage evaluation of wet-chemical silicon-wafer thinning process. 3DIC Naoya Watanabe, Takumi Miyazaki, Masahiro Aoyagi, Kazuhiro Yoshikawa
2011	—	`conf`	Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integration. 3DIC Fumiki Kato, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi
2011	—	`conf`	PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. 3DIC Katsuya Kikuchi, Chihiro Ueda, Fumiaki Fujii, Yutaka Akiyama, Naoya Watanabe, Yasuhiro Kitamura, Toshio Gomyo, Toshikazu Okubo, Tetsuya Koyama, Tadashi Kamada, Masahiro Aoyagi, Kanji Otsuka
2009	—	`conf`	SrTiO3 thin film decoupling capacitors on Si interposers for 3D system integration. 3DIC Koichi Takemura, Katsuya Kikuchi, Chihiro Ueda, Kazuhiro Baba, Masahiro Aoyagi, Kanji Otsuka
2009	—	`conf`	Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substrates. 3DIC Katsuya Kikuchi, Koichi Takemura, Chihiro Ueda, Osamu Shimada, Toshio Gomyo, Yukiharu Takeuchi, Toshikazu Okubo, Kazuhiro Baba, Masahiro Aoyagi, Toshio Sudo, Kanji Otsuka
2008	J	`jnl`	Chemical flip-chip bonding method for fabricating 10-µm-pad-pitch interconnect. IEICE Electron. Express Yasuhiro Yamaji, Tokihiko Yokoshima, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi
2006	J	`jnl`	Band-Stop Filter Effect of Power/Ground Plane on Through-Hole Signal Via in Multilayer PCB. IEICE Trans. Electron. Junso Pak, Masahiro Aoyagi, Katsuya Kikuchi, Joungho Kim
1991	J	`jnl`	A fully operational 1 kb variable threshold Josephson RAM. IEEE J. Solid State Circuits Itaru Kurosawa, Hiroshi Nakagawa, Masahiro Aoyagi, Shin Kosaka, Susumu Takada
1990	J	`jnl`	A Josephson 10-b instruction 128-word ROM unit. IEEE J. Solid State Circuits Masahiro Aoyagi, Hiroshi Nakagawa, Itaru Kurosawa, Shin Kosaka, Yoshikuni Okada, Youichi Hamazaki, Susumu Takada
1989	J	`jnl`	A 1 kbit Josephson random access memory using variable threshold cells. IEEE J. Solid State Circuits Itaru Kurosawa, Hiroshi Nakagawa, Shin Kosaka, Masahiro Aoyagi, Susumu Takada
1989	J	`jnl`	A Josephson 4 bit RALU for a prototype computer. IEEE J. Solid State Circuits Hiroshi Nakagawa, Shin Kosaka, Hiroki Kawamura, Itaru Kurosawa, Masahiro Aoyagi, Youichi Hamazaki, Yoshikuni Okada, Susumu Takada