Masahiko Yoshimoto

198 papers A 4B 3C 19Misc 4Journal 86Unranked 82

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	A 1.15-TOPS 6.57-TOPS/W DNN Processor for Multi-Scale Object Detection. AICAS Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2020	J	`jnl`	A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations. IEEE J. Sel. Top. Signal Process. Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Go Matsukawa, Toshio Goto, Motoshi Kojima
2020	—	`conf`	An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. AICAS Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto
2020	J	`jnl`	Heartbeat Interval Error Compensation Method for Low Sampling Rates Photoplethysmography Sensors. IEICE Trans. Commun. Kento Watanabe, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2019	J	`jnl`	A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2019	—	`conf`	A Heartbeat Interval Error Compensation Method Using Multiple Linear Regression for Photoplethysmography Sensors. BioCAS Seiya Yoshida, Shintaro Izumi, Yuki Nishikawa, Kento Watanabe, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2019	—	`conf`	A Low-Power Photoplethysmography Sensor using Correlated Double Sampling and Reference Readout Circuit. IEEE SENSORS Kana Sasai, Shintaro Izumi, Kento Watanabe, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2019	—	`conf`	An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. A-SSCC Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto
2019	J	`jnl`	Energy-Efficient Spectral Analysis Method Using Autoregressive Model-Based Approach for Internet of Things. IEEE Trans. Circuits Syst. I Regul. Pap. Seiya Yoshida, Shintaro Izumi, Koichi Kajihara, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2019	J	`jnl`	Low-Noise Photoplethysmography Sensor Using Correlated Double Sampling for Heartbeat Interval Acquisition. IEEE Trans. Biomed. Circuits Syst. Kento Watanabe, Shintaro Izumi, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2019	J	`jnl`	Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare. J. Signal Process. Syst. Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2019	J	`jnl`	Non-Contact Instantaneous Heart Rate Extraction System Using 24-GHz Microwave Doppler Sensor. IEICE Trans. Commun. Shintaro Izumi, Takaaki Okano, Daichi Matsunaga, Hiroshi Kawaguchi, Masahiko Yoshimoto
2019	J	`jnl`	Recent Progress of Biomedical Processor SoC for Wearable Healthcare Application: A Review. IEICE Trans. Electron. Masahiko Yoshimoto, Shintaro Izumi
2018	—	`conf`	28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning. ICECS Haruki Mori, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2018	J	`jnl`	A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate. IEICE Trans. Electron. Motofumi Nakanishi, Shintaro Izumi, Mio Tsukahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto
2018	J	`jnl`	A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668]. IEICE Electron. Express Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto
2018	—	`conf`	Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning. SiPS Kazuki Yamada, Haruki Mori, Tetsuya Youkawa, Yuki Miyauchi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2018	—	`conf`	Delayed Weight Update for Faster Convergence in Data-Parallel Deep Learning. GlobalSIP Tetsuya Youkawa, Haruki Mori, Yuki Miyauchi, Kazuki Yamada, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2018	—	`conf`	Hardware Implementation of Autoregressive Model Estimation Using Burg's Method for Low-Energy Spectral Analysis. SiPS Koichi Kajihara, Shintaro Izumi, Seiya Yoshida, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2018	—	`conf`	Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth. ICECS Yuki Miyauchi, Haruki Mori, Tetsuya Youkawa, Kazuki Yamada, Shintato Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Atsuki Inoue
2018	C	`conf`	Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring. ISCAS Yuki Nishikawa, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2017	—	`conf`	A 19-μA metabolic equivalents monitoring SoC using adaptive sampling. ASP-DAC Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori
2017	—	`conf`	A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning. MLSP Haruki Mori, Tetsuya Youkawa, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Atsuki Inoue
2017	J	`jnl`	A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video. IEICE Electron. Express Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto
2017	—	`conf`	A swallowable sensing device platform with wireless power feeding and chemical reaction actuator. EMBC Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto
2017	—	`conf`	Capacitively coupled ECG sensor system with digitally assisted noise cancellation for wearable application. BioCAS Yuki Nagasato, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2017	—	`conf`	FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature. SiPS Yuri Nishizumi, Go Matsukawa, Koichi Kajihara, Taisuke Kodama, Shintaro Izumi, Hiroshi Kawaguchi, Chikako Nakanishi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto
2017	—	`conf`	Multimodal cardiovascular information monitor using piezoelectric transducers for wearable healthcare. SiPS Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2017	—	`conf`	Non-contact biometric identification and authentication using microwave Doppler sensor. BioCAS Takaaki Okano, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2017	—	`conf`	Wearable pulse wave velocity sensor using flexible piezoelectric film array. BioCAS Takumi Katsuura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Shusuke Yoshimoto, Tsuyoshi Sekitani
2016	—	`conf`	A 15-μA metabolic equivalents monitoring system using adaptive acceleration sampling and normally off computing. ICECS Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori
2016	J	`jnl`	A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor. IEICE Trans. Electron. Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2016	J	`jnl`	A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. IPSJ Trans. Syst. LSI Des. Methodol. Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
2016	—	`conf`	Adaptive noise cancellation method for capacitively coupled ECG sensor using single insulated electrode. BioCAS Yoshito Tanaka, Shintaro Izumi, Yuta Kawamoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2016	—	`conf`	An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology. ICECS Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2016	C	`conf`	An soft error propagation analysis considering logical masking effect on re-convergent path. IOLTS Shuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2016	—	`conf`	Capacitively coupled ECG sensor using a single electrode with adaptive power-line noise cancellation. BHI Yuta Kawamoto, Shintaro Izumi, Yoshito Tanaka, Hiroshi Kawaguchi, Masahiko Yoshimoto
2016	J	`jnl`	Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Go Matsukawa, Yuta Kimi, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2016	—	`conf`	Low-power metabolic equivalents estimation algorithm using adaptive acceleration sampling. EMBC Mio Tsukahara, Motofumi Nakanishi, Shintaro Izumi, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2016	C	`conf`	Non-contact Instantaneous Heart Rate Monitoring Using Microwave Doppler Sensor and Time-Frequency Domain Analysis. BIBE Daichi Matsunaga, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2016	—	`conf`	Swallowable sensing device for long-term gastrointestinal tract monitoring. EMBC Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto
2015	—	`conf`	A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems. ASP-DAC Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2015	—	`conf`	A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. CICC Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2015	J	`jnl`	A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Okuno, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Masahiko Yoshimoto
2015	J	`jnl`	A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. IEICE Trans. Electron. Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi, Masahiko Yoshimoto
2015	J	`jnl`	A Wearable Healthcare System With a 13.7 µ A Noise Tolerant ECG Processor. IEEE Trans. Biomed. Circuits Syst. Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2015	—	`conf`	A ferroelectric-based non-volatile flip-flop for wearable healthcare systems. NVMTS Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori
2015	C	`conf`	A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. ISCAS Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto
2015	—	`conf`	A more acceptable endoluminal implantation for remotely monitoring ingestible sensors anchored to the stomach wall. EMBC Hidetoshi Ohta, Shintaro Izumi, Masahiko Yoshimoto
2015	—	`conf`	A negative-resistance sense amplifier for low-voltage operating STT-MRAM. ASP-DAC Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
2015	J	`jnl`	An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter. IEICE Trans. Electron. Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2015	C	`conf`	An accurate soft error propagation analysis technique considering temporal masking disablement. IOLTS Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2015	—	`conf`	Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path. ATS Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2015	—	`conf`	Large displacement haptic stimulus actuator using piezoelectric pump for wearable devices. EMBC Taisuke Kodama, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Kazusuke Maenaka, Masahiko Yoshimoto
2015	J	`jnl`	Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2015	J	`jnl`	Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems. IEICE Trans. Inf. Syst. Shintaro Izumi, Masanao Nakano, Ken Yamashita, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2015	—	`conf`	Non-contact and noise tolerant heart rate monitoring using microwave doppler sensor and range imagery. EMBC Daichi Matsunaga, Shintaro Izumi, Keisuke Okuno, Hiroshi Kawaguchi, Masahiko Yoshimoto
2015	J	`jnl`	Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector. IEEE Trans. Biomed. Circuits Syst. Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2015	—	`conf`	Physical activity group classification algorithm using triaxial acceleration and heart rate. EMBC Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hironori Sato, Hiroshi Kawaguchi, Masahiko Yoshimoto, Takafumi Ando, Satoshi Nakae, Chiyoko Usui, Tomoko Aoyama, Shigeho Tanaka
2014	—	`conf`	A 2.23 ps RMS jitter 3 μs fast settling ADPLL using temperature compensation PLL controller. ICECS Keisuke Okuno, Kana Masaki, Shintaro Izumi, Toshihiro Konishi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	—	`conf`	A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability. A-SSCC Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	J	`jnl`	A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	—	`conf`	A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	J	`jnl`	A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI. IEICE Electron. Express Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	—	`conf`	A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems. BioCAS Shintaro Izumi, Ken Yamashita, Masanao Nakano, Tomoki Nakagawa, Yuki Kitahara, Koji Yanagida, Shusuke Yoshimoto, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2014	C	`conf`	A 6T-4C shadow memory using plate line and word line boosting. ISCAS Tomoki Nakagawa, Shintaro Izumi, Shusuke Yoshimoto, Koji Yanagida, Yuki Kitahara, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	—	`conf`	A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM. ARCS Workshops Go Matsukawa, Yohei Nakata, Yuta Kimi, Yasuo Sugure, Masafumi Shimozawa, Shigeru Oho, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	J	`jnl`	A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI. J. Signal Process. Syst. Kenta Takagi, Kotaro Tanaka, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	—	`conf`	An 8-bit I/O-sized ADC with second-order TDC and MOM capacitor voltage-to-time converter. ICECS Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2014	—	`conf`	Noise tolerant QRS detection using template matching with short-term autocorrelation. EMBC Yozaburo Nakai, Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	—	`conf`	Normally-off technologies for healthcare appliance. ASP-DAC Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Yoshikazu Fujimori
2014	J	`jnl`	STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
2014	J	`jnl`	Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	—	`conf`	A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system. ESSCIRC Shintaro Izumi, Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2013	J	`jnl`	A 168-mW 2.4X-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI. IEICE Trans. Electron. Guangji He, Takanobu Sugahara, Yuki Miyamoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	—	`conf`	A 38 μA wearable biosignal monitoring system with near field communication. NEWCAS Ken Yamashita, Shintaro Izumi, Masanao Nakano, Takahide Fujii, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2013	—	`conf`	A 40-NM 54-MW 3×-real-time VLSI processor for 60-kWord continuous speech recognition. SiPS Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	—	`conf`	A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	—	`conf`	A 40-nm 144-mW VLSI processor for real-time 60-kWord continuous speech recognition. ASP-DAC Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	—	`conf`	A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. CICC Shusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	J	`jnl`	A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops. IEICE Trans. Electron. Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2013	J	`jnl`	A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video. IEICE Trans. Electron. Kosuke Mizuno, Kenta Takagi, Yosuke Terachi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	—	`conf`	A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. ASP-DAC Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	Misc	`conf`	A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection. ICASSP Kenta Takagi, Kosuke Mizuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	J	`jnl`	An FPGA Implementation of a HOG-based Object Detection Processor. IPSJ Trans. Syst. LSI Des. Methodol. Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	J	`jnl`	An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2013	—	`conf`	Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags. ISQED Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi
2013	J	`jnl`	Foreword. IEICE Trans. Electron. Masahiko Yoshimoto
2013	C	`conf`	Low-power hardware implementation of noise tolerant heart rate extractor for a wearable monitoring system. BIBE Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	J	`jnl`	Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	—	`conf`	Noise-tolerant instantaneous heart rate and R-peak detection using short-term autocorrelation for wearable healthcare systems. EMBC Takahide Fujii, Masanao Nakano, Ken Yamashita, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	J	`jnl`	Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM. IEICE Trans. Electron. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	—	`conf`	Temperature compensation using least mean squares for fast settling all-digital phase-locked loop. NEWCAS Keisuke Okuno, Shintaro Izumi, Toshihiro Konishi, Song Dae-Woo, Masahiko Yoshimoto, Hiroshi Kawaguchi
2012	J	`jnl`	0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. Inf. Media Technol. Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. IPSJ Trans. Syst. LSI Des. Methodol. Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. IEICE Trans. Electron. Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi
2012	J	`jnl`	A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. Guangji He, Takanobu Sugahara, Yuki Miyamoto, Tsuyoshi Fujinaga, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Trans. Electron. Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	—	`conf`	A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition. CICC Guangji He, Takanobu Sugahara, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	—	`conf`	A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. IEICE Electron. Express Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	A	`conf`	A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	C	`conf`	A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping. ISCAS Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2012	—	`conf`	A 61-dB SNDR 700 µm VLSIC Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2012	—	`conf`	A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator. NEWCAS Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2012	J	`jnl`	A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing. IEICE Trans. Electron. Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	—	`conf`	Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection. SiPS Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	—	`conf`	Bit error rate estimation in SRAM considering temperature fluctuation. ISQED Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi
2012	J	`jnl`	Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes. IEICE Trans. Commun. Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
2012	J	`jnl`	Foreword. IEICE Trans. Electron. Masahiko Yoshimoto
2012	Misc	`conf`	Handsfree Voice Interface for Home Network Service Using a Microphone Array Network. ICNC Shinpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	C	`conf`	Implementing Virtual Agent as an Interface for Smart Home Voice Control. APSEC Shinpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	—	`conf`	Instantaneous Heart Rate detection using short-time autocorrelation for wearable healthcare systems. EMBC Masanao Nakano, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy. IEICE Electron. Express Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. IEICE Trans. Electron. Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	C	`conf`	Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	—	`conf`	Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores. ARCS Workshops Koji Kugata, Shinpei Soda, Yohei Nakata, Shunsuke Okumura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011	—	`conf`	0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM. ISQED Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011	—	`conf`	256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V. ICECS Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	J	`jnl`	7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	—	`conf`	A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10 ESSCIRC Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	—	`conf`	A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition. CICC Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	C	`conf`	A 40-nm 640-µm ISCAS Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011	J	`jnl`	A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshihiro Konishi, Shintaro Izumi, Koh Tsuruda, Hyeokjong Lee, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011	J	`jnl`	A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011	J	`jnl`	A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition. IEICE Trans. Electron. Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	C	`conf`	A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers. DSD Yohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	—	`conf`	Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. ISQED Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	B	`conf`	Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network. ICCCN Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shinpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011	J	`jnl`	Data-Intensive Sound Acquisition System with Large-scale Microphone Array. Inf. Media Technol. Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011	J	`jnl`	Data-Intensive Sound Acquisition System with Large-scale Microphone Array. J. Inf. Process. Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011	J	`jnl`	Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. Inf. Media Technol. Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	J	`jnl`	Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. IPSJ Trans. Syst. LSI Des. Methodol. Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	—	`conf`	Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. CICC Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	—	`conf`	Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units. DSN Workshops Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	C	`conf`	Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	J	`jnl`	VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition. IEICE Trans. Electron. Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010	A	`conf`	0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. ISLPED Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010	—	`conf`	7T SRAM enabling low-energy simultaneous block copy. CICC Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010	—	`conf`	A 34.7-mW quad-core MIQP solver processor for robot control. CICC Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010	J	`jnl`	A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design. IEICE Trans. Electron. Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
2010	J	`jnl`	A power-variation model for sensor node and the impact against life time of wireless sensor networks. IEICE Electron. Express Takashi Matsuda, Takashi Takeuchi, Takefumi Aonishi, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
2010	B	`conf`	Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video. FPL Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010	C	`conf`	Intelligent ubiquitous sensor network for sound acquisition. ISCAS Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2010	C	`conf`	Live demonstration: Intelligent ubiquitous sensor network for sound acquisition. ISCAS Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2010	C	`conf`	Parallel-processing VLSI architecture for mixed integer linear programming. ISCAS Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009	—	`conf`	A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009	J	`jnl`	A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks. IEICE Trans. Electron. Takashi Takeuchi, Shinji Mikami, Hyeokjong Lee, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
2009	Misc	`conf`	A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. VLSI Design Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009	J	`jnl`	A Dependable SRAM with 7T/14T Memory Cells. IEICE Trans. Electron. Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009	—	`conf`	An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks. SiPS Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2009	A	`conf`	Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system. INTERSPEECH Tsuyoshi Fujinaga, Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008	J	`jnl`	A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Trans. Electron. Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008	J	`jnl`	A Sub 100 mW H.264 [email protected] Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer. IEICE Trans. Electron. Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008	J	`jnl`	A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. IEICE Trans. Electron. Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto
2008	—	`conf`	A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system. FPT Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008	C	`conf`	A sub 100 mW H.264/AVC [email protected] integer-pel motion estimation processor VLSI for MBAFF encoding. ISCAS Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008	—	`conf`	An H.264/AVC [email protected] quarter-pel motion estimation processor VLSI for real-time MBAFF encoding. ICECS Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008	J	`jnl`	Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks. IEICE Trans. Commun. Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
2008	J	`jnl`	Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock. IEICE Trans. Commun. Takashi Takeuchi, Yu Otake, Masumi Ichien, Akihiro Gion, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
2008	J	`jnl`	Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. Very Large Scale Integr. Syst. Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008	—	`conf`	Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
2007	—	`conf`	A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2007	J	`jnl`	Area Comparison between 6T and 8T SRAM Cells in Dual- IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2007	J	`jnl`	Area Optimization in 6T and 8T SRAM Cells Considering IEICE Trans. Electron. Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2007	J	`jnl`	Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks. IEICE Trans. Commun. Takashi Matsuda, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
2007	B	`conf`	Delay Guarantee and Service Interval Optimization for HCCA in IEEE 802.11e WLANs. WCNC Yuhi Higuchi, Augusto Foronda, Chikara Ohta, Masahiko Yoshimoto, Yoji Okada
2007	—	`conf`	Multipath Routing using Isochronous Medium Access Control with Multi Wakeup Period for Wireless Sensor Networks. ISWCS Takashi Matsuda, Takafumi Aonishi, Takashi Takeuchi, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
2007	—	`conf`	Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture. ASP-DAC Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto
2007	J	`jnl`	Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE 802.11e WLANs. IEICE Trans. Commun. Augusto Foronda, Yuhi Higuchi, Chikara Ohta, Masahiko Yoshimoto, Yoji Okada
2006	J	`jnl`	A 0.3-V Operating, IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2006	J	`jnl`	A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kentaro Kawakami, Jun Takemura, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto
2006	J	`jnl`	A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90NM Risc Processor. Intell. Autom. Soft Comput. Kentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Hideo Ohira, Masayuki Miyama, Masahiko Yoshimoto
2006	C	`conf`	A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. VLSI-SoC Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno
2006	J	`jnl`	A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing. IEICE Trans. Electron. Junichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto
2006	J	`jnl`	A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto
2006	A	`conf`	A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
2006	J	`jnl`	Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks. IEICE Trans. Commun. Shinji Mikami, Takafumi Aonishi, Hironori Yoshino, Chikara Ohta, Hiroshi Kawaguchi, Masahiko Yoshimoto
2006	—	`conf`	Impact of Aggregation Efficiency on GIT Routing forWireless Sensor Networks. ICPP Workshops Takafumi Aonishi, Takashi Matsuda, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
2006	J	`jnl`	VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation. IEICE Trans. Electron. Noriyuki Minegishi, Junichi Miyakoshi, Yuki Kuroda, Tadayoshi Katagiri, Yuki Fukuyama, Ryo Yamamoto, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto
2005	J	`jnl`	A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto
2005	J	`jnl`	A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. IEICE Trans. Electron. Junichi Miyakoshi, Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto
2005	J	`jnl`	Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Masayuki Miyama, Masahiko Yoshimoto
2004	—	`conf`	A sub-mW MPEG-4 motion estimation processor core for mobile video application. ASP-DAC Yuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto
2004	J	`jnl`	A sub-mW MPEG-4 motion estimation processor core for mobile video application. IEEE J. Solid State Circuits Masayuki Miyama, Junichi Miyakoshi, Yuki Kuroda, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto
2003	—	`conf`	A sub-mW MPEG-4 motion estimation processor core for mobile video application. CICC Junichi Miyakoshi, Yuri Kuroda, Masayuki Miyama, Kosuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto
2003	J	`jnl`	A world first development of a multipoint videophone system over 3G-324M protocol. Int. J. Mob. Commun. Hideo Ohira, Mitsuru Kodama, Masahiko Yoshimoto
2003	J	`jnl`	The development and impact on business of the world's first live video streaming distribution platform for 3G mobile videophone terminals. Int. J. Electron. Bus. Hideo Ohira, Mitsuru Kodama, Masahiko Yoshimoto
2002	—	`conf`	An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. CICC Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto
2001	—	`conf`	An image sensor with fast extraction of objects' positions - rough vision processor. ICIP (2) Akira Watanabe, Osamu Tooyama, Masayuki Miyama, Masahiko Yoshimoto, Junichi Akita
2000	C	`conf`	MPEG-2 4: 2: 2@HL encoder chip set. ISCAS Hidenori Sato, Hideo Ohira, Masahiko Kazayama, Ayako Harada, Masahiko Yoshimoto, Okikazu Tanno, Satoshi Kumaki, Kazuya Ishibara, Atsuo Hanami, Tetsuya Mutsumura
2000	—	`conf`	Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video. CICC T. Kamemaru, Hideo Ohira, H. Suzuki, Ken'ichi Asano, Masahiko Yoshimoto, Tokumichi Murakami
1995	J	`jnl`	A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search. IEEE J. Solid State Circuits Kazuya Ishihara, Shinichi Masuda, Shin-ichi Hattori, Hirofumi Nishikawa, Yoshihide Ajioka, Tsuyoshi Yamada, Hiroyuki Amishiro, Shin-ichi Uramoto, Masahiko Yoshimoto, Tadashi Sumi
1995	Misc	`conf`	A highly-parallel DSP architecture for image recognition. ICASSP Hiroyuki Kawai, Yoshitugu Inoue, Robert Streitenberger, Masahiko Yoshimoto
1992	J	`jnl`	A 100-MHz 2-D discrete cosine transform core processor. IEEE J. Solid State Circuits Shin-ichi Uramoto, Yoshitsugu Inoue, Akihiko Takabatake, Jun Takeda, Yukihiro Yamashita, Hideyuki Terane, Masahiko Yoshimoto
1990	J	`jnl`	A 24-b 50-ns digital image signal processor. IEEE J. Solid State Circuits Shin-ichi Nakagawa, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shuichi Kato, Masahiro Hatanaka, Hideo Ohira, Yoshiaki Kato, Mamoru Iwatsuki, Kinya Tabuchi, Yasutaka Horiba