Masahide Takada

13 papers A 1Journal 12

Year	Rank	Type	Title / Venue / Authors
1996	J	`jnl`	A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM. IEEE J. Solid State Circuits Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki
1996	J	`jnl`	A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme. IEEE J. Solid State Circuits Hiraki Koike, Tetsuya Otsuki, Tohru Kimura, Masao Fukuma, Yoshihiro Hayashi, Yukihiko Maejima, Kazushi Amanuma, Nobuhira Tanabe, Takeo Matsuki, Shinobu Saito, Tsuneo Takeuchi, Souta Kobayashi, Takemitsu Kunio, Takashi Hase, Yoichi Miyasaka, Nobuaki Shohata, Masahide Takada
1996	J	`jnl`	A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump. IEEE J. Solid State Circuits Hitoshi Okamura, Takao Atsumo, Koichi Takeda, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Tom Yamazaki
1995	J	`jnl`	A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. IEEE J. Solid State Circuits Hitoshi Okamura, Hideo Toyoshima, Koichi Takeda, Takashi Oguri, Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Hiroshi Yoshida, Tom Yamazaki
1994	J	`jnl`	A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator. IEEE J. Solid State Circuits Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki
1993	J	`jnl`	A 300-MHz 16-b BiCMOS video signal processor. IEEE J. Solid State Circuits Toshiaki Inoue, Junichi Goto, Masakazu Yamashina, Kazumasa Suzuki, Masahiro Nomura, Youichi Koseki, Tohru Kimura, Takao Atsumo, Masato Motomura, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada, Masahide Takada
1993	J	`jnl`	Memory LSI reliability. Proc. IEEE Masao Fukuma, Hiroshi Furuta, Masahide Takada
1992	J	`jnl`	A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. IEEE J. Solid State Circuits Akira Tanabe, Toshio Takeshima, Hiroki Koike, Yoshiharu Aimoto, Masahide Takada, Toshiyuki Ishijima, Naoki Kasai, Hiromitsu Hada, Kentaro Shibahara, Takemitsu Kunio, Takaho Tanigawa, Takanori Saeki, Masato Sakao, Hidenobu Miyamoto, Hiroshi Nozue, Shuichi Ohya, Tatsunori Murotani, Kuniaki Koyama, Takashi Okuda
1992	J	`jnl`	A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM. IEEE J. Solid State Circuits Kazuyuki Nakamura, Takashi Oguri, Takao Atsumo, Masahide Takada, Atsushi Ikemoto, Hisamitsu Suzuki, Tadashi Nishigori, Tohru Yamazaki
1990	J	`jnl`	A 5-ns 1-Mb ECL BiCMOS SRAM. IEEE J. Solid State Circuits Masahide Takada, Kazuyuki Nakamura, Toshio Takeshima, Koichiro Furuta, Tohru Yamazaki, Kiyotaka Imai, Susumu Ohi, Yumi Sekine, Yukio Minato, Hisamitsu Kimuto
1990	J	`jnl`	A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM. IEEE J. Solid State Circuits Toshio Takeshima, Masahide Takada, Hiroki Koike, Hiroshi Watanabe, Shigeru Koshimaru, Kenjiro Mitake, Wataru Kikuchi, Takaho Tanigawa, Tatsunori Murotani, Kenji Noda, Kazuhiro Tasaka, Koji Yamanaka, Kuniaki Koyama
1990	A	`conf`	A BIST scheme using microprogram ROM for large capacity memories. ITC Hiroki Koike, Toshio Takeshima, Masahide Takada
1988	J	`jnl`	Voltage limiters for DRAMs with substrate-plate-electrode memory cells. IEEE J. Solid State Circuits Toshio Takeshima, Masahide Takada, Toshiyuki Shimizu, Takuya Katoh, Mitsuru Sakamoto