Masaharu Imai - RankMe

91 papers A* 2A 6C 7Misc 4Journal 28Unranked 43

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	EMoDi: Entity-Enhanced Momentum-Difference Contrastive Learning for Semantic-Aware Verification of Scientific Information. ICKG Ze Yang, Yimeng Sun, Takao Nakaguchi, Masaharu Imai
2018	J	`jnl`	Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koichi Mitsunari, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu
2017	J	`jnl`	A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems. J. Inf. Process. Tomoki Sugiura, Masaharu Imai, Jaehoon Yu, Yoshinori Takeuchi
2017	J	`jnl`	Deformable Part Model Based Arrhythmia Detection Using Time Domain Features. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuuka Hirao, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu
2017	—	`conf`	Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface. ASP-DAC Masaharu Imai, Yoshinori Takeuchi, Jun Ohta, Gregg Jørgen Suaning, Chung-Yu Wu, Napoleon Torres-Martinez
2017	—	`conf`	Flexible sensor sheet for real-time pressure monitoring in artificial knee joint during total knee arthroplasty. EMBC Fumika Tanabe, Shusuke Yoshimoto, Yuki Noda, Teppei Araki, Takafumi Uemura, Yoshinori Takeuchi, Masaharu Imai, Tsuyoshi Sekitani
2016	—	`conf`	A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis. BioCAS Tomoki Sugiura, Arif Ullah Khan, Jaehoon Yu, Yoshinori Takeuchi, Seiji Kameda, Takatsugu Kamata, Yuki Hayashida, Tetsuya Yagi, Masaharu Imai
2015	—	`conf`	A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems. BioCAS Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai
2015	J	`jnl`	An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC. Inf. Media Technol. Salita Sombatsiri, Yoshinori Takeuchi, Masaharu Imai
2015	J	`jnl`	An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC. IPSJ Trans. Syst. LSI Des. Methodol. Salita Sombatsiri, Yoshinori Takeuchi, Masaharu Imai
2015	—	`conf`	Cortical neural excitations in rats in vivo with using a prototype of a wireless multi-channel microstimulation system. EMBC Yuki Hayashida, Yuichi Umehira, Kouki Takatani, Shigetoshi Futami, Seiji Kameda, Takatsugu Kamata, Arif Ullah Khan, Yoshinori Takeuchi, Masaharu Imai, Tetsuya Yagi
2015	—	`conf`	Preliminary study of a new home healthcare monitoring to prevent the recurrence of stroke. EMBC Toshiyo Tamura, Masaki Sekine, Zunyi Tang, Masaki Yoshida, Yoshinori Takeuchi, Masaharu Imai
2014	J	`jnl`	A New Available Bandwidth Estimation Method Using RTT for a Bottleneck Link. IEICE Trans. Commun. Masaharu Imai, Yoshio Sugizaki, Koichi Asatani
2014	—	`conf`	An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology. BioCAS Tomoki Sugiura, Shoko Nakatsuka, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai
2013	—	`conf`	A new estimation method using RTT for available bandwidth of a bottleneck link. ICOIN Masaharu Imai, Yoshio Sugizaki, Koichi Asatani
2013	—	`conf`	An efficient lossless data compression method based on exponential-Golomb coding for biomedical information and its implementation using ASIP technology. BioCAS Shoko Nakatsuka, Takashi Hamabe, Yoshinori Takeuchi, Masaharu Imai
2013	J	`jnl`	Electronic triage system for continuously monitoring casualties at disaster scenes. J. Ambient Intell. Humaniz. Comput. Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka
2013	C	`conf`	Error analysis of an estimation method using RTT for available bandwidth of a bottleneck link. APNOMS Masaharu Imai, Takayuki Ozawa, Yoshio Sugizaki, Koichi Asatani
2012	J	`jnl`	A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring. IEICE Trans. Electron. Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2012	—	`conf`	On-chip Communication Buffer Architecture Optimization Considering Bus Width. MCSoC Salita Sombatsiri, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2012	—	`conf`	Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion. MCSoC Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2011	—	`conf`	Automated architecture exploration for low energy reconfigurable AGU. ISOCC Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2011	—	`conf`	Biological information sensing technologies for medical, health care, and wellness applications. ASP-DAC Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato
2011	—	`conf`	Electronic Triage System: Casualties Monitoring System in the Disaster Scene. 3PGCIC Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka
2011	J	`jnl`	Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2010	J	`jnl`	A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions. Inf. Media Technol. Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2010	J	`jnl`	A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions. IPSJ Trans. Syst. LSI Des. Methodol. Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2010	—	`conf`	A new compilation technique for SIMD code generation across basic block boundaries. ASP-DAC Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto, Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai
2010	J	`jnl`	Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). Inf. Media Technol. Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura
2010	J	`jnl`	Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). IPSJ Trans. Syst. LSI Des. Methodol. Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura
2010	C	`conf`	Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm. ISCAS Hassan A. Youness, Abdel-Moniem Wahdan, Mohammed Hassan, Ashraf Salem, Mohammed Moness, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2010	J	`jnl`	Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors. IPSJ Trans. Syst. LSI Des. Methodol. Takahiro Kumura, Soichiro Taga, Nagisa Ishiura, Yoshinori Takeuchi, Masaharu Imai
2010	—	`conf`	Two-stage configurable decoder model for multiple forward error correction standards. ESTIMedia Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2009	J	`jnl`	Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2009	J	`jnl`	Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hassan A. Youness, Keishi Sakanushi, Yoshinori Takeuchi, Ashraf Salem, Abdel-Moniem Wahdan, Masaharu Imai
2009	J	`jnl`	Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai
2009	—	`conf`	Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. ASP-DAC Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2008	J	`jnl`	Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
2008	—	`conf`	Operation shuffling over cycle boundaries for low energy L0 clustering. ASAP Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
2007	—	`conf`	A Block-Floating-Point Processor for Rapid Application Development. ICASSP (2) Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Shiro Kobayashi
2007	—	`conf`	A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. ASP-DAC Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2007	Misc	`conf`	A low power VLIW processor generation method by means of extracting non-redundant activation conditions. CODES+ISSS Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2007	J	`jnl`	Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto
2007	J	`jnl`	Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. ACM Trans. Design Autom. Electr. Syst. Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
2007	J	`jnl`	RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC CoRR M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2006	—	`conf`	Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model. VLSI-SoC (Selected Papers) Ittetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai
2006	Misc	`conf`	Pack instruction generation for media pUsing multi-valued decision diagram. CODES+ISSS Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa
2006	C	`conf`	Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. VLSI-SoC Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2005	—	`conf`	Enabling RTOS simulation modeling in a system level design language. ASP-DAC M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2005	—	`conf`	Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. ESTIMedia Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
2005	A	`ed.`	Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005 ESA Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic
2005	A	`conf`	RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. DATE M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2005	—	`conf`	Verification Challenges in Configurable Processor Design with ASIP Meister. CHARME Masaharu Imai, Akira Kitajima
2004	A	`conf`	Architecture-Level Performance Estimation for IP-Based Embedded Systems. DATE Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2004	—	`ed.`	Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 ASP-DAC Masaharu Imai
2004	—	`conf`	S-sequence: a new floorplan representation method preserving room abutment relationships. ISCAS (4) Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai
2004	—	`conf`	Synthesizable HDL generation method for configurable VLIW processors. ASP-DAC Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2004	—	`conf`	Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation. ICDCS Workshops H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2003	C	`conf`	A Code Selection Method for SIMD Processors with PACK Instructions. SCOPES Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai
2003	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masaharu Imai
2003	—	`conf`	Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III. ICASSP (2) Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai
2003	A	`conf`	Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III. ICME Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai
2002	J	`jnl`	A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai
2002	C	`conf`	Design of Application Specific CISC Using PEAS-III. IEEE International Workshop on Rapid System Prototyping Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai
2002	Misc	`conf`	Design space exploration for DSP applications using the ASIP development system PEAS-III. ICASSP Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai
2001	—	`conf`	Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. ASP-DAC Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai
2001	—	`conf`	VLSI Implementation of Fractal Image Compression Processor for Moving Pictures. EUROMICRO Hideki Yamauchi, Yoshinori Takeuchi, Masaharu Imai
2000	—	`conf`	One language or more?: how can we design an SoC at a system level? ASP-DAC Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura
2000	C	`conf`	PEAS-III: An ASIP Design Environment. ICCD Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi
1999	Misc	`conf`	A programmable processor with multiple functional units and banked registers for general purpose numerical processing. ICASSP Takafumi Morifuji, Yoshinori Takeuchi, Masaharu Imai
1999	—	`conf`	Application of FHM-Based Design Method to Scalable 2-D DCT Processor. EUROMICRO Eiichirou Shigehara, Yoshinori Takeuchi, Masaharu Imai, Tsutomu Kimura
1998	—	`conf`	A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. ASP-DAC Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi
1997	—	`conf`	VLSI implementation of a real-time operating system. ASP-DAC Takumi Nakano, Yoshiki Komatsudaira, Akichika Shiomi, Masaharu Imai
1996	A*	`conf`	A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. DAC Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi
1996	—	`conf`	A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs. EURO-DAC Masaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi
1996	J	`jnl`	ASPDAC 1995: HDL synthesizability and interoperability. IEEE Des. Test Comput. Masaharu Imai, Eugenio Villar
1996	J	`jnl`	VLSI implementation and evaluation of a real-time operating system. Syst. Comput. Jpn. Takumi Nakano, Andy Utama, Akichika Shiomi, Masaharu Imai, Mitsuyoshi Itabashi
1995	—	`conf`	A hardware/software codesign method for pipelined instruction set processor using adaptive database. ASP-DAC Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi
1995	—	`conf`	A hardware/software partitioning algorithm for pipelined instruction set processor. EURO-DAC Nguyen-Ngoc Bình, Masaharu Imai, Nobuyuki Hikichi
1995	—	`conf`	Future direction of synthesizability and interoperability of HDL's: part 1. ASP-DAC Masaharu Imai, Eugenio Villar
1995	—	`conf`	Future direction of synthesizabilty and interoperability of HDL's: part 2. ASP-DAC Eugenio Villar, Masaharu Imai
1993	A	`conf`	An ASIP instruction set optimization algorithm with functional module sharing constraint. ICCAD Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi
1993	—	`conf`	PEAS-I: A hardware/software co-design system for ASIPs. EURO-DAC Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Jun Sato, Nobuyuki Hikichi, Masaharu Imai
1992	—	`conf`	An integer programming approach to instruction implementation method selection problem. EURO-DAC Masaharu Imai, Jun Sato, Alauddin Alomary, Nobuyuki Hikichi
1991	C	`conf`	An Integrated Design Environment for Application Specific Integrated Processor. ICCD Jun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi
1988	J	`jnl`	Computational complexity of the file allocation problem in distributed database systems. Syst. Comput. Jpn. Hiroshi Yamasaki, Tomio Hirata, Masaharu Imai, Toshihide Ibaraki
1988	J	`jnl`	Reconfiguration of a fault-tolerant rectangular systolic array. Syst. Comput. Jpn. Yoshinao Suzuki, Tomio Hirata, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki
1987	J	`jnl`	Parallel searches of game trees. Syst. Comput. Jpn. Hiromoto Usui, Masafumi Yamashita, Masaharu Imai, Toshihide Ibaraki
1986	—	`conf`	Implementation of Parallel Prolog on Tree Machines. FJCC Hajime Miura, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki
1984	A	`conf`	The Architecture and Efficiency of DON: A Combinatorial Problem Oriented Multicomputer System. ICDCS Masaharu Imai, Yuuji Tateizumi, Yuuji Yoshida, Teruo Fukumura
1979	A*	`conf`	A Parallel Searching Scheme for Multiprocessor Systems and Its Application to Combinatorial Problems. IJCAI Masaharu Imai, Yuuji Yoshida, Teruo Fukumura