Masafumi Nogawa

13 papers C 2Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2017 C conf
25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.
ISCAS
Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka
2015 — conf
A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking.
A-SSCC
Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura
2014 C conf
20.1-mW 8-Gbps UWB-IR millimeter-wave transmitter using an OOK pulse modulator based on CMOS inverters.
ISCAS
Shinsuke Nakano, Hiroaki Katsurai, Minoru Togashi, Hiroshi Koizumi, Masafumi Nogawa
2013 — conf
F3: Emerging technologies for wireline communication.
ISSCC
Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi
2013 — conf
Session 7 overview: Optical transceivers and silicon photonics.
ISSCC
Ichiro Fujimori, Masafumi Nogawa
2013 J jnl
Small and Low-Cost Dual-Rate Optical Triplexer for OLT Transceivers in 10G/1G Co-existing 10G-EPON Systems.
IEICE Trans. Electron.
Atsushi Kanda, Akira Ohki, Takeshi Kurosaki, Hiroaki Sanjoh, Kota Asaka, Ryoko Yoshimura, Toshio Ito, Makoto Nakamura, Masafumi Nogawa, Yusuke Ohtomo, Mikio Yoneyama
2012 — conf
A 10Gb/s burst-mode laser diode driver for burst-by-burst power saving.
ISSCC
Hiroshi Koizumi, Minoru Togashi, Masafumi Nogawa, Yusuke Ohtomo
2008 J jnl
A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs.
IEICE Trans. Electron.
Yusuke Ohtomo, Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minoru Togashi, Kiyomi Kumozaki
2008 J jnl
A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI.
IEICE Trans. Electron.
Yusuke Ohtomo, Hiroshi Koizumi, Kazuyoshi Nishimura, Masafumi Nogawa
2006 — conf
A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOS.
ISSCC
Masafumi Nogawa, Yusuke Ohtomo, Shunji Kimura, Kazuyoshi Nishimura, Tomoaki Kawamura, Minoru Togashi
2006 J jnl
A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS.
IEEE J. Solid State Circuits
Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa
1998 J jnl
A data-transition look-ahead DFF circuit for statistical reduction in power consumption.
IEEE J. Solid State Circuits
Masafumi Nogawa, Yusuke Ohtomo
1994 J jnl
BiCMOS circuit technology for a 704 MHz ATM switch LSI.
IEEE J. Solid State Circuits
Yusuke Ohtomo, Sadayuki Yasuda, Minoru Togashi, Massyuki Ino, Yasuyuki Tanabe, Jun-ichi Inoue, Masafumi Nogawa, Sshigeki Hino