| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2011 | J | jnl |
Int. J. Circuit Theory Appl.
|
| 2006 | B | conf |
IJCNN
|
| 2004 | J | jnl |
IEEE Multim.
|
| 2002 | J | jnl |
J. VLSI Signal Process.
|
| 2002 | J | jnl |
Neural Networks
|
| 2001 | J | jnl |
J. Parallel Distributed Comput.
|
| 2001 | J | jnl |
IEEE Trans. Neural Networks
|
| 2001 | J | jnl |
Auton. Robots
|
| 2000 | — | conf |
ISMVL
|
| 1999 | J | jnl |
IEEE Trans. Biomed. Eng.
|
| 1999 | — | conf |
IPPS/SPDP
|
| 1999 | J | jnl |
IEEE Trans. Neural Networks
|
| 1998 | — | conf |
NIPS
|
| 1998 | A | conf |
ISLPED
|
| 1998 | J | jnl |
Pattern Recognit. Lett.
|
| 1998 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 1997 | — | conf |
NIPS
|
| 1996 | J | jnl |
Appl. Intell.
|
| 1995 | — | conf |
NIPS
|
| 1995 | J | jnl |
IEEE J. Solid State Circuits
|
| 1995 | J | jnl |
IEEE Trans. Neural Networks
|
| 1995 | J | jnl |
IEEE Micro
|
| 1995 | J | jnl |
Neural Process. Lett.
|
| 1995 | C | conf |
ISCAS
|
| 1994 | J | jnl |
VLSI Design
|
| 1994 | — | conf |
NIPS
|
| 1994 | — | conf |
NIPS
|
| 1993 | J | jnl |
J. VLSI Signal Process.
|
| 1993 | — | conf |
ANNES
|
| 1993 | — | conf |
NIPS
|
| 1993 | — | conf |
ANNES
|
| 1993 | J | jnl |
Int. J. Neural Syst.
|
| 1993 | — | conf |
NIPS
|
| 1992 | A | conf |
ICCAD
|
| 1992 | J | jnl |
IEEE Trans. Neural Networks
|
| 1992 | — | conf |
NIPS
|
| 1992 | J | jnl |
IEEE Trans. Neural Networks
|
| 1991 | — | conf |
NIPS
|
| 1991 | J | jnl |
Neural Comput.
|
| 1990 | A* | conf |
DAC
|
| 1989 | Misc | conf |
ICASSP
|
| 1989 | J | jnl |
Knowl. Based Syst.
|
| 1989 | A* | conf |
DAC
|
| 1989 | J | jnl |
IEEE Expert
|
| 1989 | J | jnl |
Review of Design Automation: Automated Full-Custom VLSI Layout Using the Ulysses Design Environment.
AI Mag.
|
| 1988 | A* | conf |
DAC
|
| 1987 | J | jnl |
Artif. Intell. Eng.
|