Martín Vázquez

13 papers Journal 11Unranked 2
YearRankTypeTitle / Venue / Authors
2024 J jnl
Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding.
J. Supercomput.
Marcelo Tosini, Martín Vázquez, Lucas Leiva
2024 J jnl
Automated Parasite Control System Prototype Through Capsule Dosage Based on Image Processing.
IEEE Embed. Syst. Lett.
Ezequiel Carbajo, Lucas Leiva, Juan Toloza, Martín Vázquez, Silvina Fernández, Federica Sagües, Milagros Junco, Inés Guerrero, Sara Zegbi, Carlos Saumell
2024 J jnl
Automatic Fecal Eggs Counting in Ruminants Using Xilinx DPU.
IEEE Embed. Syst. Lett.
Lucas Leiva, Bruno Constanzo, Martín Vázquez, Juan Manuel Toloza
2023 J jnl
FPGA-Based Accelerator for AI-Toolbox Reinforcement Learning Library.
IEEE Embed. Syst. Lett.
Lucas Leiva, Jordina Torrents-Barrena, Martín Vázquez
2022 J jnl
FPGA acceleration analysis of LibSVM predictors based on high-level synthesis.
J. Supercomput.
Lucas Leiva, Martín Vázquez, Jordina Torrents-Barrena
2021 J jnl
Radix-10 Restoring Square Root for 6-input LUTs Programmable Devices.
Circuits Syst. Signal Process.
Martín Vázquez, Marcelo Tosini, Lucas Leiva
2019 J jnl
Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices.
Microprocess. Microsystems
Martín Vázquez, Lucas Leiva, Gustavo Sutter
2016 J jnl
Real-time speckle image processing.
J. Real Time Image Process.
Elias Todorovich, Ana Lucía Dai Pra, Lucía Isabel Passoni, Martín Vázquez, Ezequiel Cozzolino, Fernando Ferrara, Gery Bioul
2012 J jnl
Correction to "Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course".
IEEE Trans. Educ.
Elias Todorovich, José A. Marone, Martín Vázquez
2012 J jnl
Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course.
IEEE Trans. Educ.
Elias Todorovich, José A. Marone, Martín Vázquez
2010 J jnl
High-Speed FPGA 10's Complement Adders-Subtractors.
Int. J. Reconfigurable Comput.
Gery Bioul, Martín Vázquez, Jean-Pierre Deschamps, Gustavo Sutter
2009 — conf
Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations.
ReConFig
Martín Vázquez, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps
2009 — conf
FPGA Implementations of BCD Multipliers.
ReConFig
Gustavo Sutter, Elias Todorovich, Gery Bioul, Martín Vázquez, Jean-Pierre Deschamps