Martti Forsell

70 papers A 2B 1C 5Misc 7Journal 16Unranked 35

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	Preliminary Performance and Memory Access Scalability Study of Thick Control Flow Processors. NorCAS Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
2023	J	`jnl`	Realizing multioperations and multiprefixes in Thick Control Flow processors. Microprocess. Microsystems Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
2022	J	`jnl`	Performance and programmability comparison of the thick control flow architecture and current multicore processors. J. Supercomput. Martti Forsell, Sara Nikula, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
2020	—	`conf`	Optimizing Memory Access in TCF Processors with Compute-Update Operations. IPDPS Workshops Martti Forsell, Jussi Roivainen, Jesper Larsson Träff
2018	—	`conf`	Implementation of Multioperations in Thick Control Flow Processors. IPDPS Workshops Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
2018	J	`jnl`	REPLICA MBTAC: multithreaded dual-mode processor. J. Supercomput. Martti Forsell, Jussi Roivainen, Ville Leppänen
2018	—	`ch.`	Reducing Power Consumption in Mobile Terminals - Video Computing Perspective. Greening Video Distribution Networks Martti Forsell
2018	J	`jnl`	Supporting concurrent memory access in TCF processor architectures. Microprocess. Microsystems Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
2018	—	`conf`	Towards Energy-Efficient Adaptive Mpeg-Dash Streaming Using Hevc. ICME Workshops Mikko Uitto, Martti Forsell
2017	—	`conf`	Supporting concurrent memory access in TCF-aware processor architectures. NORCAS Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
2017	—	`conf`	Towards a Language Framework for Thick Control Flows. IPDPS Workshops Jari-Matti Mäkelä, Martti Forsell, Ville Leppänen
2016	—	`conf`	A study on energy used to deliver H.264/AVC and H.265/HEVC video content. CAMAD Mohammadhassan Safavi, Saeed Bastani, Zhi Zhang, Martti Forsell, Olli Mämmelä, Björn Landfeldt
2016	—	`conf`	Compiler assisted dynamic allocation of finite hardware acceleration resources for parallel tasks. CompSysTech Jari-Matti Mäkelä, Martti Forsell, Ville Leppänen
2016	—	`conf`	Outline of a Thick Control Flow Architecture. SBAC-PAD (Workshops) Martti Forsell, Jussi Roivainen, Ville Leppänen
2016	—	`conf`	The REPLICA on-chip network. NORCAS Martti Forsell, Jussi Roivainen, Ville Leppänen
2015	B	`conf`	Cost of Bandwidth-Optimized Sparse Mesh Layouts. PaCT Martti Forsell, Ville Leppänen, Martti Penttonen
2014	—	`conf`	A Quantitative Comparison of PRAM based Emulated Shared Memory Architectures to Current Multicore CPUs and GPUs. ARCS Workshops Erik Hansson, Erik Alnervik, Christoph W. Keßler, Martti Forsell
2014	C	`conf`	Exploration of a Heterogeneous Concentrated-Sparse On-Chip Interconnect for Energy Efficient Multicore Architecture. CIT Thomas Canhao Xu, Ville Leppänen, Martti Forsell
2014	J	`jnl`	NUMA Computing with Hardware and Software Co-Support on Configurable Emulated Shared Memory Architectures. Int. J. Netw. Comput. Martti Forsell, Erik Hansson, Christoph W. Kessler, Jari-Matti Mäkelä, Ville Leppänen
2014	—	`conf`	Prototyping the MBTAC Processor for the REPLICA CMP. IPDPS Workshops Martti Forsell, Jussi Roivainen, Ville Leppänen
2014	Misc	`conf`	REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor. ACSSC Martti Forsell, Jussi Roivainen
2013	J	`jnl`	An Extended PRAM-NUMA Model of Computation for TCF Programming. Int. J. Netw. Comput. Martti Forsell, Ville Leppänen
2013	C	`conf`	DSNOC: A Hybrid Dense-Sparse Network-on-Chip Architecture for Efficient Scalable Computing. DASC Thomas Canhao Xu, Ville Leppänen, Martti Forsell
2013	—	`conf`	Hardware and Software Support for NUMA Computing on Configurable Emulated Shared Memory Architectures. IPDPS Workshops Martti Forsell, Erik Hansson, Christoph W. Kessler, Jari-Matti Mäkelä, Ville Leppänen
2013	—	`conf`	Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture. CompSysTech Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell
2012	—	`conf`	An Extended PRAM-NUMA Model of Computation for TCF Programming. IPDPS Workshops Martti Forsell, Ville Leppänen
2012	C	`conf`	Design of the Language Replica for Hybrid PRAM-NUMA Many-core Architectures. ISPA Jari-Matti Mäkelä, Erik Hansson, Daniel Åkesson, Martti Forsell, Christoph W. Kessler, Ville Leppänen
2012	—	`conf`	Multi-core Portability Abstraction. IPDPS Workshops Martti Forsell, Mikko Hiivala
2012	—	`conf`	Preliminary analysis of feasible benchmark problems for the hydrid PRAM/NUMA REPLICA architecture. CompSysTech Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell
2011	J	`jnl`	A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads. Int. J. Netw. Comput. Martti Forsell
2011	—	`conf`	A layout for sparse cube-connected-cycles network. CompSysTech Ville Leppänen, Martti Penttonen, Martti Forsell
2011	J	`jnl`	A moving threads processor architecture MTPA. J. Supercomput. Martti Forsell, Ville Leppänen
2011	C	`conf`	Cost of Sparse Mesh Layouts Supporting Throughput Computing. DSD Martti Forsell, Ville Leppänen, Martti Penttonen
2011	J	`jnl`	Performance comparison of some shared memory organizations for 2D mesh-like NOCs. Microprocess. Microsystems Martti Forsell
2011	—	`conf`	RISC-based moving threads multicore architecture. CompSysTech Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell
2010	—	`conf`	A PRAM-NUMA model of computation for addressing low-TLP workloads. IPDPS Workshops Martti Forsell
2010	—	`ed.`	Euro-Par 2009 - Parallel Processing Workshops, HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25-28, 2009, Revised Selected Papers Euro-Par Workshops Hai-Xiang Lin, Michael Alexander, Martti Forsell, Andreas Knüpfer, Radu Prodan, Leonel Sousa, Achim Streit
2010	—	`conf`	HPPC 2010: 5th Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops (1) Martti Forsell, Jesper Larsson Träff
2010	—	`conf`	HPPC 2010: Forth Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops Martti Forsell, Jesper Larsson Träff
2010	Misc	`conf`	Layouts for Sparse Networks Supporting Throughput Computing. PDPTA Ville Leppänen, Martti Penttonen, Martti Forsell
2010	J	`jnl`	On the Performance and Cost of Some PRAM Models on CMP Hardware. Int. J. Found. Comput. Sci. Martti Forsell
2010	Misc	`conf`	Supporting Concurrent Memory Access and Multioperations in Moving Threads CMPs. PDPTA Martti Forsell, Ville Leppänen
2009	—	`conf`	Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. NOCS Martti Forsell
2009	—	`conf`	HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? Euro-Par Workshops Martti Forsell, H. Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff
2009	—	`conf`	HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops Martti Forsell, Jesper Larsson Träff
2009	Misc	`conf`	MTPA - A Processor Architecture for MP-SOCs Employing the Moving Threads Paradigm. PDPTA Martti Forsell, Ville Leppänen
2009	—	`conf`	Outline of RISC-based core for multiprocessor on chip architecture supporting moving threads. CompSysTech Jani Paakkulainen, Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell
2008	—	`ed.`	Euro-Par 2007 Workshops: Parallel Processing, HPPC 2007, UNICORE Summit 2007, and VHPC 2007, Rennes, France, August 28-31, 2007, Revised Selected Papers Euro-Par Workshops Luc Bougé, Martti Forsell, Jesper Larsson Träff, Achim Streit, Wolfgang Ziegler, Michael Alexander, Stephen Childs
2008	A	`conf`	On the performance and cost of some PRAM models on CMP hardware. IPDPS Martti Forsell
2008	Misc	`conf`	Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architectures. PDPTA Martti Forsell, Jussi Roivainen
2008	—	`conf`	Second Workshop on Highly Parallel Processing on a Chip (HPPC 2008). Euro-Par Workshops Martti Forsell, Jesper Larsson Träff
2007	—	`conf`	HPPC 2007: Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops Martti Forsell, Jesper Larsson Träff
2007	Misc	`conf`	Moving Threads: A Non-Conventional Approach for Mapping Computation to MP-SOC. PDPTA Martti Forsell, Ville Leppänen
2006	—	`conf`	Realizing Multioperations for Step Cached MP-SOCs. SoC Martti Forsell
2006	A	`conf`	Reducing the associativity and size of step caches in CRCW operation. IPDPS Martti Forsell
2005	—	`conf`	ParLe - A Parallel Computing Learning Set for MPSOCs/NOCs. SoC Martti Forsell
2005	J	`jnl`	Realising constant time parallel algorithms with active memory modules. Int. J. Electron. Bus. Martti Forsell
2004	C	`conf`	Designing NOCs with a parallel extension of c. FDL Martti Forsell
2004	—	`conf`	Ec - a compiler for the e-language [NOC applications]. SoC Martti Forsell
2004	—	`conf`	Efficient barrier synchronization mechanism for emulated shared memory NOCs. SoC Martti Forsell
2003	—	`ch.`	A Parallel Computer as a NOC Region. Networks on Chip Martti Forsell
2003	Misc	`conf`	Extending Platform-Based Design to Network on Chip Systems. VLSI Design Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar
2002	—	`conf`	A Network on Chip Architecture and Design Methodology. ISVLSI Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani
2002	J	`jnl`	A Scalable High-Performance Computing Solution for Networks on Chips. IEEE Micro Martti Forsell
2002	J	`jnl`	Architectural differences of efficient sequential and parallel computers. J. Syst. Archit. Martti Forsell
2002	J	`jnl`	Context-based compression of binary images in parallel. Softw. Pract. Exp. Eugene I. Ageenko, Martti Forsell, Pasi Fränti
2002	—	`conf`	Fast processor core selection for WLAN modem using mappability estimation. CODES Juha-Pekka Soininen, Jari Kreku, Yang Qu, Martti Forsell
1997	J	`jnl`	MTAC - A Multithreaded VLIW Architecture for PRAM Simulation. J. Univers. Comput. Sci. Martti Forsell
1996	—	`conf`	Efficient Two-Level Mesh based Simulation of PRAMs. ISPAN Martti Forsell, Martti Penttonen, Ville Leppänen
1996	J	`jnl`	Minimal pipeline architecture - an alternative to superscalar architecture. Microprocess. Microsystems Martti Forsell