Martin Radetzki

83 papers A 7B 1C 25Misc 1Journal 15Unranked 31

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Pipelined Scheduling and Communication Synthesis for Application-Specific Networks-on-Chip. MCSoC Martin Radetzki
2024	—	`conf`	Integer Linear Programming Based Design of Deadlock-Free Routing for Chiplet-Based Systems. SOCC Shuang Liu, Martin Radetzki
2024	—	`conf`	Synergistic Floorplanning and Routing Topology Co-design for Application-Specific NoC Synthesis. MCSoC Shuang Liu, Martin Radetzki
2023	—	`conf`	Systematic Construction of Deadlock-Free Routing for NoC Using Integer Linear Programming. MCSoC Shuang Liu, Martin Radetzki
2021	—	`conf`	Comprehensive modeling and evaluation of Network-on-Chip performability. MBMV Jie Hou, Martin Radetzki
2019	C	`conf`	A Backend Tool for the Integration of Memory Optimizations into Embedded Software. FDL Manuel Strobel, Martin Radetzki
2019	—	`conf`	A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs. MCSoC Jie Hou, Qi Han, Martin Radetzki
2019	C	`conf`	A methodology to compute long-term fault resilience of NoCs under fault-tolerant routing algorithms. FDL Jie Hou, Martin Radetzki
2019	—	`conf`	Automated Sensor Firmware Development - Generation, Optimization, and Analysis. MBMV Jens Rudolf, Manuel Strobel, Joscha Benz, Christian Haubelt, Martin Radetzki, Oliver Bringmann
2019	—	`conf`	Combined MPSoC Task Mapping and Memory Optimization for Low-Power. APCCAS Manuel Strobel, Gereon Führ, Martin Radetzki, Rainer Leupers
2019	—	`conf`	Design-Time Memory Subsystem Optimization for Low-Power Multi-Core Embedded Systems. MCSoC Manuel Strobel, Martin Radetzki
2019	J	`jnl`	Power-mode-aware Memory Subsystem Optimization for Low-power System-on-Chip Design. ACM Trans. Embed. Comput. Syst. Manuel Strobel, Martin Radetzki
2018	C	`conf`	Performability Analysis of Mesh-Based NoCs Using Markov Reward Model. PDP Jie Hou, Martin Radetzki
2017	—	`conf`	Hybrid instruction set simulation for fast and accurate memory access profiling. WISES Manuel Strobel, Martin Radetzki
2017	J	`jnl`	Low power memory allocation and mapping for area-constrained systems-on-chips. EURASIP J. Embed. Syst. Manuel Strobel, Marcus Eggenberger, Martin Radetzki
2017	J	`jnl`	Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. IEEE Trans. Computers Gert Schley, Atefe Dalirsani, Marcus Eggenberger, Nadereh Hatami, Hans-Joachim Wunderlich, Martin Radetzki
2017	Misc	`conf`	Semi-symbolic operational computation for robust control system design. MMAR Leandro Gil, Martin Radetzki
2016	C	`conf`	Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures. PDP Marcus Eggenberger, Manuel Strobel, Martin Radetzki
2016	A	`conf`	Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation. DATE Leandro Gil, Martin Radetzki
2016	J	`jnl`	Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy. Comput. Electr. Eng. Gert Schley, Ibrahim Ahmed, Muhammad Afzal, Martin Radetzki
2015	C	`conf`	Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip. PDP Gert Schley, Martin Radetzki
2015	—	`conf`	Multi-Layer Test and Diagnosis for Dependable NoCs. NOCS Hans-Joachim Wunderlich, Martin Radetzki
2015	—	`conf`	Optimal memory selection for low power embedded systems. WISES Marcus Eggenberger, Martin Radetzki
2014	C	`conf`	A comparison of parallel systemc simulation approaches at RTL. FDL Bastian Haetzer, Martin Radetzki
2014	—	`conf`	Asynchronous parallel simulation with transaction events. ICSAMOS Bastian Haetzer, Martin Radetzki
2014	J	`jnl`	Editorial introduction - Special issue on languages, models and model based design for embedded systems. Des. Autom. Embed. Syst. Martin Radetzki, Axel Jantsch
2014	—	`conf`	On Covering Structural Defects in NoCs by Functional Tests. ATS Atefe Dalirsani, Nadereh Hatami, Michael E. Imhof, Marcus Eggenberger, Gert Schley, Martin Radetzki, Hans-Joachim Wunderlich
2014	C	`conf`	SystemC AMS power electronic modeling with ideal instantaneous switches. FDL Leandro Gil, Martin Radetzki
2013	J	`jnl`	Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation. Microprocess. Microsystems Weiyun Lu, Martin Radetzki
2013	C	`conf`	Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip. PDP Gert Schley, Nikolaos Batzolis, Martin Radetzki
2013	C	`conf`	Fine grained adaptive simulation with application to NoCs. FDL Marcus Eggenberger, Martin Radetzki
2013	J	`jnl`	Methods for fault tolerance in networks-on-chip. ACM Comput. Surv. Martin Radetzki, Chaochao Feng, Xueqian Zhao, Axel Jantsch
2013	J	`jnl`	Optimal placement of vertical connections in 3D Network-on-Chip. J. Syst. Archit. Thomas Canhao Xu, Gert Schley, Pasi Liljeberg, Martin Radetzki, Juha Plosila, Hannu Tenhunen
2013	J	`jnl`	Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip. J. Electron. Test. Khalid Latif, Amir-Mohammad Rahmani, Ethiopia Nigussie, Tiberiu Seceleanu, Martin Radetzki, Hannu Tenhunen
2013	C	`conf`	Platform based design. FDL Jean-Philippe Babau, Martin Radetzki
2013	—	`conf`	Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors. GreenCom/iThings/CPScom Adán Kohler, Martin Radetzki
2013	—	`conf`	Scalable parallel simulation of networks on chip. NOCS Marcus Eggenberger, Martin Radetzki
2013	C	`conf`	Simulation analysis and validation. FDL Frank Oppenheimer, Martin Radetzki
2013	C	`conf`	Systemc transaction level modeling with transaction events. FDL Bastian Haetzer, Martin Radetzki
2012	—	`conf`	Latency-optimized Collectives for High Performance on Intel's Single-chip Cloud Computer. MARC@RWTH Adán Kohler, Martin Radetzki
2012	C	`conf`	Low-Latency Collectives for the Intel SCC. CLUSTER Adán Kohler, Martin Radetzki, Philipp Gschwandtner, Thomas Fahringer
2012	C	`conf`	Minimal MPI as programming interface for multicore System-on-Chips. FDL Adán Kohler, Juan Manuel Castillo-Sanchez, Joachim Gross, Martin Radetzki
2012	—	`conf`	Optimized Reduce for Mesh-Based NoC Multiprocessors. IPDPS Workshops Adán Kohler, Martin Radetzki
2012	J	`jnl`	Semantics and efficient simulation of accuracy-adaptive TLMs. Des. Autom. Embed. Syst. Rauf Salimi Khaligh, Martin Radetzki
2011	C	`conf`	A case study on message-based discrete event simulation for Transaction Level Modeling. FDL Bastian Haetzer, Martin Radetzki
2011	C	`conf`	A metamodel and semantics for transaction level modeling. FDL Rauf Salimi Khaligh, Martin Radetzki
2011	—	`ch.`	Cost-Based Deflection Routing for Intelligent NoC Switches. Solutions on Embedded Systems Martin Radetzki, Adán Kohler
2011	C	`conf`	Efficient Fault Simulation of SystemC Designs. DSD Weiyun Lu, Martin Radetzki
2011	C	`conf`	Fault-Tolerant Differential Q Routing in Arbitrary NoC Topologies. EUC Martin Radetzki
2011	—	`conf`	Optimal distribution of privileged nodes in networks-on-chip. WISES Gert Schley, Martin Radetzki
2011	—	`conf`	Practical embedded systems engineering syllabus for graduate students with multidisciplinary backgrounds. WESE Bastian Haetzer, Gert Schley, Rauf Salimi Khaligh, Martin Radetzki
2010	C	`conf`	A Dynamic Load Balancing Method for Parallel Simulation of Accuracy Adaptive TLMs. FDL Rauf Salimi Khaligh, Martin Radetzki
2010	J	`jnl`	Degradability Enabled Routing for Network-on-Chip Switches (Routingverfahren zur Unterstützung der Degradierbarkeit von Network-on-Chip Switches). it Inf. Technol. Gert Schley, Martin Radetzki, Adán Kohler
2010	J	`jnl`	Fault Tolerant Network on Chip Switching With Graceful Performance Degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Adán Kohler, Gert Schley, Martin Radetzki
2010	A	`conf`	Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs. DATE Rauf Salimi Khaligh, Martin Radetzki
2009	C	`conf`	A SystemC TLM2 model of communication in wormhole switched Networks-On-Chip. FDL Adán Kohler, Martin Radetzki
2009	—	`conf`	An intelligent deflection router for networks-on-chip. WISES Martin Radetzki, Adán Kohler
2009	—	`conf`	Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling. IESS Rauf Salimi Khaligh, Martin Radetzki
2009	—	`conf`	Fault-tolerant architecture and deflection routing for degradable NoC switches. NOCS Adán Kohler, Martin Radetzki
2009	—	`ed.`	Languages for Embedded Systems and their Applications - Selected Contributions on Specification, Design, and Verification from FDL'08, September 23-25, 2008, Stuttgart, Germany FDL (Selected Papers) Martin Radetzki
2009	—	`conf`	Modellierung und Simulation von Networks-on-Chip mit OSCI TLM2. MBMV Adán Kohler, Martin Radetzki
2009	A	`conf`	Test exploration and validation using transaction level models. DATE Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto
2008	C	`conf`	A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses. FDL Rauf Salimi Khaligh, Martin Radetzki
2008	C	`conf`	A data traffic efficient H.264 deblocking IP. ISCAS Weining Hao, Martin Radetzki
2008	A	`conf`	Accuracy-Adaptive Simulation of Transaction Level Models. DATE Martin Radetzki, Rauf Salimi Khaligh
2008	—	`conf`	Adaptive Interconnect Models for Transaction-Level Simulation. FDL (Selected Papers) Rauf Salimi Khaligh, Martin Radetzki
2007	—	`conf`	Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions. IESS Rauf Salimi Khaligh, Martin Radetzki
2007	—	`conf`	Modellierung auf der Transaktionsebene unter Nutzung des Entwurfsmusters des aktiven Objekts. MBMV Martin Radetzki
2007	C	`conf`	Modelling Alternatives for Cycle Approximate Bus TLMs. FDL Martin Radetzki, Rauf Salimi Khaligh
2006	C	`conf`	SystemC TLM Transaction Modelling and Dispatch for Active Object. FDL Martin Radetzki
2004	—	`conf`	IPQ: IP Qualification for Efficient System Design. ISQED Hans-Jürgen Brand, Steffen Rülke, Martin Radetzki
2004	J	`jnl`	Intelligent IP retrieval driven by application requirements. Integr. Martin Schaaf, Andrea Freßmann, Rainer Maximini, Ralph Bergmann, Alexander Tartakovski, Martin Radetzki
2004	A	`conf`	Measurement of IP Qualification Costs and Benefits. DATE Andreas Vörg, Martin Radetzki, Wolfgang Rosenstiel
2003	C	`conf`	sciPROVE: C++ Based Verification Environment for IP and SoC Design1. FDL U. Badelt, H. Kühl, Martin Radetzki
2002	—	`conf`	A Qualification Platform for Design Reuse. ISQED Ralf Seepold, Natividad Martínez Madrid, Andreas Vörg, Wolfgang Rosenstiel, Martin Radetzki, Peter Neumann, Jürgen Haase
2002	J	`jnl`	Qualität und Qualitätssicherung wiederverwendbarer Schaltungsbeschreibungen (Quality and Quality Assurance of Reusable Circuit Descriptions). Informationstechnik Tech. Inform. Martin Radetzki
2000	—	`—`	Synthesis of digital circuits from object oriented specifications. Martin Radetzki
1999	A	`conf`	Data Type Analysis for Hardware Synthesis from Object-Oriented Models. DATE Martin Radetzki, Ansgar Stammermann, Wolfram Putzke-Röming, Wolfgang Nebel
1998	A	`conf`	A Flexible Message Passing Mechanism for Objective VHDL. DATE Wolfram Putzke-Röming, Martin Radetzki, Wolfgang Nebel
1998	J	`jnl`	A Unified Approach to Object-Oriented VHDL. J. Inf. Sci. Eng. Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel
1998	—	`conf`	ATM Cell Modelling using Objective VHDL. ASP-DAC Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki
1998	—	`conf`	Übersetzung von Objektorientiertem VHDL nach Standard VHDL. MBMV Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel
1996	B	`conf`	Development of a Telephone Answering Machine in a Lab - FPGAs in Education. FPL Guido Schumacher, Bernhard Josko, Gerhard Wagner, Martin Radetzki