Martin Margala

190 papers A 6B 7C 23Misc 6Journal 58Unranked 86

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Cybersecurity meets carbon neutrality: Strategies for sustainable data center security operations. Sustain. Comput. Informatics Syst. Thomas Samraj Lawrence, Martin Margala, S. Siva Shankar, Prasun Chakrabarti, G. Nagarajan
2026	J	`jnl`	DPC-Net: Dense Pyramid CAViaR Network for gastric cancer detection with lymph node segmentation using histopathological image. Biomed. Signal Process. Control. Santhosh Kumar Balan, Martin Margala, Prasun Chakrabarti, Mohammed Ali Hussain
2026	J	`jnl`	DeepWebnet analytics enhancing dark web surveillance for effective cyber threat detection and mitigation. Inf. Secur. J. A Glob. Perspect. S. Yogesh Kumaran, B. Sivaneasan, S. Siva Shankar, Prasun Chakrabarti, Tulika Chakrabarti, Martin Margala
2026	J	`jnl`	Guest Editorial: Special Issue on Intelligence of Social Things-Enabled Cooperative Learning for Behavioral-Cultural Modeling. IEEE Trans. Comput. Soc. Syst. Chinmay Chakraborty, Bhuvan Unhelkar, Saïd Mahmoudi, Martin Margala, Sayonara Barbosa
2025	J	`jnl`	Corrections to "IoT-Enabled Advanced Water Quality Monitoring System for Pond Management and Environmental Conservation". IEEE Access Jeetendra Kumar, Rashmi Gupta, Suvarna Sharma, Tulika Chakrabarti, Prasun Chakrabarti, Martin Margala
2025	J	`jnl`	Enhance the growth of agriculture by predicting crop diseases using optimization and deep learning. Int. J. Syst. Assur. Eng. Manag. T. Sathish Kumar, Martin Margala, S. Siva Shankar, Prasun Chakrabarti
2025	J	`jnl`	Enhanced Task Scheduling in Cloud Computing Using the ESRNN Algorithm: A Performance-Driven Approach. Internet Technol. Lett. Chintureena Thingom, Martin Margala, S. Siva Shankar, Prasun Chakrabarti, R. G. Vidhya
2025	J	`jnl`	Heart disease prediction using spark architecture with fused feature set and hybrid Squeezenet-Linknet model. Biomed. Signal Process. Control. Parvathaneni Rajendra Kumar, Prasun Chakrabarti, Tulika Chakrabarti, Bhuvan Unhelkar, Martin Margala
2025	J	`jnl`	Hyper-Embedded Computing: An Optimized System Architecture for Area-Constrained Applications. IEEE Embed. Syst. Lett. Boisy Gene Pitre, Martin Margala, Kevin J. Phillipson, Michael G. Rywalt
2025	—	`conf`	HyperEncoding: Spiking Neural Networks with Hyperdimensional Encoding for Robust Edge Intelligence. ACM Great Lakes Symposium on VLSI Alaaddin Goktug Ayar, Anthony Maida, Martin Margala
2025	C	`conf`	ML4FPGA: An LLM Framework for Electronic Design Automation and Verification on FPGA. VLSI-SoC Uchechukwu Leo Udeji, Martin Margala
2025	—	`conf`	Single-Pass Symbolic Learning for Real-Time Embedded Security. ACM Great Lakes Symposium on VLSI Alaaddin Goktug Ayar, Sercan Aygun, Martin Margala
2025	C	`conf`	TLGLock: A New Approach in Logic Locking Using Key-Driven Charge Recycling in Threshold Logic Gates. VLSI-SoC Abdullah Sahruri, Martin Margala
2025	J	`jnl`	TLGLock: A New Approach in Logic Locking Using Key-Driven Charge Recycling in Threshold Logic Gates. CoRR Abdullah Sahruri, Martin Margala
2024	J	`jnl`	A trust-centric approach to intrusion detection in edge networks for medical internet of thing Ecosystems. Comput. Electr. Eng. G. Nagarajan, Martin Margala, S. Siva Shankar, Prasun Chakrabarti, R. I. Minu
2024	J	`jnl`	Advancing Breast Cancer Diagnosis: The Development and Validation of the HERA-Net Model for Thermographic Analysis. Comput. Mater. Continua S. Ramacharan, Martin Margala, Amjan Shaik, Prasun Chakrabarti, Tulika Chakrabarti
2024	J	`jnl`	Blockchain-Based Federated Learning Technique for Privacy Preservation and Security of Smart Electronic Health Records. IEEE Trans. Consumer Electron. Manisha Guduri, Chinmay Chakraborty, V. Uma Maheswari, Martin Margala
2024	—	`conf`	Consolidating and Optimizing Embedded Processor IP Blocks for Area, Power, and Sustainability. IGSC Boisy Gene Pitre, Martin Margala, Kevin J. Phillipson, Michael M. Rywalt
2024	J	`jnl`	Corrections to "Multi Objective Prioritized Workflow Scheduling Using Deep Reinforcement Based Learning in Cloud Computing". IEEE Access Sudheer Mangalampalli, Syed Shakeel Hashmi, Amit Gupta, Ganesh Reddy Karri, Varada Rajkumar Kukkala, Tulika Chakrabarti, Prasun Chakrabarti, Martin Margala
2024	J	`jnl`	Detecting Vulnerability in Hardware Description Languages: Opcode Language Processing. IEEE Embed. Syst. Lett. Alaaddin Goktug Ayar, Abdullah Sahruri, Sercan Aygun, Mehran Shoushtari Moghadam, M. Hassan Najafi, Martin Margala
2024	J	`jnl`	Early fire danger monitoring system in smart cities using optimization-based deep learning techniques with artificial intelligence. J. Reliab. Intell. Environ. P. Dileep Kumar Reddy, Martin Margala, S. Siva Shankar, Prasun Chakrabarti
2024	—	`conf`	HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With an Offset-Compensated Comparator. ISQED Abdullah Sahruri, Martin Margala, Ugur Çilingiroglu
2024	J	`jnl`	IoT-Enabled Advanced Water Quality Monitoring System for Pond Management and Environmental Conservation. IEEE Access Jeetendra Kumar, Rashmi Gupta, Suvarna Sharma, Tulika Chakrabarti, Prasun Chakrabarti, Martin Margala
2024	J	`jnl`	Multi Objective Prioritized Workflow Scheduling Using Deep Reinforcement Based Learning in Cloud Computing. IEEE Access Sudheer Mangalampalli, Syed Shakeel Hashmi, Amit Gupta, Ganesh Reddy Karri, Varada Rajkumar Kukkala, Tulika Chakrabarti, Prasun Chakrabarti, Martin Margala
2024	—	`conf`	SegmentAI: A Neural Net Framework for Optimized Multiclass Image Segmentation via FPGA. ISVLSI Uchechukwu Leo Udeji, Martin Margala
2024	—	`conf`	SpikeMotion: A Transformer Framework for High - Throughput Video Segmentation on FPGA. MWSCAS Uchechukwu Leo Udeji, Martin Margala
2024	—	`conf`	Word2HyperVec: From Word Embeddings to Hypervectors for Hyperdimensional Computing. ACM Great Lakes Symposium on VLSI Alaaddin Goktug Ayar, Sercan Aygun, M. Hassan Najafi, Martin Margala
2023	—	`conf`	BLTESTI: Benchmarking Lightweight TinyJAMBU on Embedded Systems for Trusted IoT. SOCC Mohamed El-Hadedy, Russell Hua, Shahzman Saqib, Kazutomo Yoshii, Wen-Mei Hwu, Martin Margala
2023	J	`jnl`	Fault-Tolerant Trust-Based Task Scheduling Algorithm Using Harris Hawks Optimization in Cloud Computing. Sensors Sudheer Mangalampalli, Ganesh Reddy Karri, Amit Gupta, Tulika Chakrabarti, Sri Hari Nallamala, Prasun Chakrabarti, Bhuvan Unhelkar, Martin Margala
2023	—	`conf`	Optimum Supply Voltage for High Gain Amplifier in Telemetry Circuitry for Ultra-Low Power Implantable Cardiac Pacemaker. NEWCAS Manisha G, Amit Krishna Dwivedi, V. Uma Maheswari, Prasun Chakrabarti, Martin Margala
2023	J	`jnl`	Prioritized Task-Scheduling Algorithm in Cloud Computing Using Cat Swarm Optimization. Sensors Sudheer Mangalampalli, Sangram Keshari Swain, Tulika Chakrabarti, Prasun Chakrabarti, Ganesh Reddy Karri, Martin Margala, Bhuvan Unhelkar, Sivaneasan Bala Krishnan
2023	—	`conf`	Quantifying the Gap between Open-Source and Vendor FPGA Place and Route Tools. HPEC Shachi Khadilkar, Ahmed Sanaullah, Martin Margala
2023	—	`conf`	RECO-LFSR: Reconfigurable Low-power Cryptographic processor based on LFSR for Trusted IoT platforms. ISQED Mohamed El-Hadedy, Russell Hua, Kazutomo Yoshii, Wen-Mei Hwu, Martin Margala
2022	—	`conf`	FPGA Implementation of Addition-based CORDIC-SNN With Izhikevich Neurons. SOCC Uchechukwu Leo Udeji, Martin Margala
2022	—	`conf`	Novel Pulse Detection System Using Differentiation: Optical Experimental Results. SOCC Sharath Patil, Bhanu Singh, Raunak Borwankar, Martin Margala
2022	—	`conf`	Novel Pulse Detection System Using Differentiation: Prototyping and Experimental Results. NEWCAS Sharath Patil, Bhanu Singh, Raunak Borwankar, Martin Margala
2022	—	`conf`	Optimizing open-source FPGA CAD tools. HPEC Shachi Khadilkar, Martin Margala
2020	—	`conf`	AutoML for Multilayer Perceptron and FPGA Co-design. SoCC Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala
2020	J	`jnl`	AutoML for Multilayer Perceptron and FPGA Co-design. CoRR Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala
2020	—	`conf`	Automated Hardware and Neural Network Architecture co-design of FPGA accelerators using multi-objective Neural Architecture Search. ICCE-Berlin Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala
2020	J	`jnl`	FPGAs for Domain Experts. Int. J. Reconfigurable Comput. Wim Vanderbauwhede, Sven-Bodo Scholz, Martin Margala
2020	—	`conf`	Functional Safety of a Lidar Sensor System. MWSCAS Sharath Patil, Bhanu Singh, Darrell Livezey, Saad Ahmad, Martin Margala
2020	—	`conf`	Micro - GAGE: A Low-power Compact GAGE Hash Function Processor for IoT Applications. ICECS Mohamed El-Hadedy, Martin Margala, Sergiu Mosanu, Danilo Gligoroski, Jinjun Xiong, Wen-Mei Hwu
2020	C	`conf`	Sparse Persistent GEMM Accelerator using OpenCL for Intel FPGAs. ISCAS Philip Colangelo, Shayan Sengupta, Martin Margala
2019	—	`conf`	Artificial Neural Network and Accelerator Co-design using Evolutionary Algorithms. HPEC Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala
2019	—	`conf`	Echo Detection Using Differentiation for Compact LIDAR Implementation. MWSCAS Sharath Patil, Volodymyr Seliuchenko, Darrell Livezey, Saad Ahmad, Bhanu Singh, Martin Margala
2019	J	`jnl`	Evolutionary Cell Aided Design for Neural Network Architectures. CoRR Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala
2018	J	`jnl`	5-Gb/s linear re-driver in 180 nm CMOS technology. Microelectron. J. Hieu Nguyen, Rod Comer, Phuc Pham, Martin Margala
2018	J	`jnl`	A Novel Terahertz Ballistic Deflection Transistor Travelling Wave Amplifier System. IEEE Trans. Circuits Syst. II Express Briefs Huan Wang, Ronald W. Knepper, Jean-François Millithaler, Martin Margala
2018	—	`conf`	A droop measurement built-in self-test circuit for digital low-dropout regulators. ISQED Aydin Dirican, Cagatay Ozmen, Martin Margala
2018	J	`jnl`	Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. CoRR Philip Colangelo, Nasibeh Nasiri, Asit K. Mishra, Eriko Nurvitadhi, Martin Margala, Kevin Nealis
2018	Misc	`conf`	Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. FCCM Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
2018	A	`conf`	Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). FPGA Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
2018	J	`jnl`	Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators. J. Electron. Test. Aydin Dirican, Cagatay Ozmen, Martin Margala
2018	—	`conf`	THz Ballistic Deflection Transistor Travelling Wave Amplifier Design with THz Ring Hybrid Coupler. NEWCAS Huan Wang, Jean-François Millithaler, Martin Margala, Ronald W. Knepper
2018	—	`conf`	Terahertz travelling wave amplifier design using Ballistic Deflection Transistor. ISQED Huan Wang, Jean-François Millithaler, Ronald W. Knepper, Martin Margala
2017	C	`conf`	A high performance Full Adder based on Ballistic Deflection Transistor technology. ISCAS Poorna Marthi, Nazir Hossain, Huan Wang, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González
2017	—	`conf`	Application of convolutional neural networks on Intel® Xeon® processor with integrated FPGA. HPEC Philip Colangelo, Enno Lübbers, Randy Huang, Martin Margala, Kevin Nealis
2017	—	`conf`	Column-wise ROIC design with on-chip calibration for photoresistive image sensor. ECCTD Cagatay Ozmen, Aydin Dirican, Hieu Nguyen, Martin Margala
2017	—	`conf`	Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits. ACM Great Lakes Symposium on VLSI Pilin Junsangsri, Fabrizio Lombardi, Salin Junsangsri, Martin Margala
2017	J	`jnl`	Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems. J. Signal Process. Syst. Mohamed El-Hadedy, Xinfei Guo, Martin Margala, Mircea R. Stan, Kevin Skadron
2017	Misc	`conf`	Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA. FCCM Philip Colangelo, Randy Huang, Enno Lübbers, Martin Margala, Kevin Nealis
2017	—	`conf`	ROIC Design for a 10k Pixel Photoresistive Image Sensor with On-Chip Calibration. NGCAS Cagatay Ozmen, Aydin Dirican, Hieu Nguyen, Martin Margala
2017	—	`conf`	Sensitivity improvement of a photoresistive image sensor with novel programmable dual element readout and calibration method. MWSCAS Cagatay Ozmen, Aydin Dirican, Hieu Nguyen, Martin Margala
2016	J	`jnl`	A CMOS Ripple Detector for Voltage Regulator Testing. J. Electron. Test. Hieu Nguyen, Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Martin Margala
2016	J	`jnl`	A Foray into Efficient Mapping of Algorithms to Hardware Platforms on Heterogeneous Systems. CoRR Oren Segal, Nasibeh Nasiri, Martin Margala
2016	C	`conf`	A new level sensitive D Latch using Ballistic nanodevices. ISCAS Poorna Marthi, Nazir Hossain, Jean-François Millithaler, Martin Margala
2016	J	`jnl`	Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations. IEEE Trans. Circuits Syst. I Regul. Pap. Poorna Marthi, Nazir Hossain, Huan Wang, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González
2016	—	`conf`	Document classification systems in heterogeneous computing environments. PATMOS Nasibeh Nasiri, Philip Colangelo, Oren Segal, Martin Margala, Wim Vanderbauwhede
2016	—	`conf`	Exploring the performance benefits of heterogeneity and reconfigurable architectures in a commodity cloud. HPCS Oren Segal, Martin Margala
2016	J	`jnl`	Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units. IEEE Trans. Very Large Scale Integr. Syst. Zhuo Qian, Martin Margala
2016	—	`conf`	Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits. ACM Great Lakes Symposium on VLSI Poorna Marthi, Sheikh Rufsan Reza, Nazir Hossain, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González
2016	—	`ed.`	Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016 ACM Great Lakes Symposium on VLSI Ayse K. Coskun, Martin Margala, Laleh Behjat, Jie Han
2015	—	`conf`	A CMOS ripple detector for integrated voltage regulator testing. DFTS Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Hieu Nguyen, Martin Margala
2015	—	`conf`	A CMOS ripple detector for integrated voltage regulator testing. MWSCAS Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Hieu Nguyen, Martin Margala
2015	A	`conf`	A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only). FPGA Zhuo Qian, Martin Margala
2015	—	`conf`	Aparapi-UCores: A high level programming framework for unconventional cores. HPEC Oren Segal, Philip Colangelo, Nasibeh Nasiri, Zhuo Qian, Martin Margala
2015	A	`conf`	High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only). FPGA Nasibeh Nasiri, Oren Segal, Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti
2015	—	`ed.`	Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015 ACM Great Lakes Symposium on VLSI Alex K. Jones, Hai (Helen) Li, Ayse K. Coskun, Martin Margala
2015	J	`jnl`	SparkCL: A Unified Programming Framework for Accelerators on Heterogeneous Clusters. CoRR Oren Segal, Philip Colangelo, Nasibeh Nasiri, Zhuo Qian, Martin Margala
2015	—	`ed.`	VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended Selected Papers VLSI-SoC (Selected Papers) Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala, Ricardo Reis
2014	—	`conf`	A novel low-power and in-place split-radix FFT processor. ACM Great Lakes Symposium on VLSI Zhuo Qian, Martin Margala
2014	B	`conf`	FPGA implementation of low-power split-radix FFT processors. FPL Zhuo Qian, Nasibeh Nasiri, Oren Segal, Martin Margala
2014	J	`jnl`	High Level Programming for Heterogeneous Architectures. CoRR Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright
2014	B	`conf`	High level programming framework for FPGAs in the data center. FPL Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright
2014	—	`conf`	High level programming of FPGAs for HPC and data centric applications. HPEC Oren Segal, Nasibeh Nasiri, Martin Margala, Wim Vanderbauwhede
2014	—	`conf`	Low power RAM-based hierarchical CAM on FPGA. ReConFig Zhuo Qian, Martin Margala
2014	—	`conf`	Modified fused multiply-accumulate chained unit. MWSCAS Nasibeh Nasiri, Oren Segal, Martin Margala
2013	C	`ed.`	21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013 VLSI-SoC Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luís Miguel Silveira, H. Fatih Ugurdag
2013	J	`jnl`	A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification. SIGARCH Comput. Archit. News Wim Vanderbauwhede, Anton Frolov, Sai Rahul Chalamalasetti, Martin Margala
2013	A	`conf`	An FPGA memcached appliance. FPGA Sai Rahul Chalamalasetti, Kevin T. Lim, Mitch Wright, Alvin AuYoung, Parthasarathy Ranganathan, Martin Margala
2013	Misc	`conf`	An IDDQ BIST approach to characterize phase-locked loop parameters. VTS Samed Maltabas, Osman Kubilay Ekekon, Kemal Kulovic, Anne Meixner, Martin Margala
2013	J	`jnl`	Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems. IEEE Trans. Very Large Scale Integr. Syst. Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede
2013	A	`conf`	High throughput filtering using FPGA-acceleration. CIKM Wim Vanderbauwhede, Anton Frolov, Leif Azzopardi, Sai Rahul Chalamalasetti, Martin Margala
2013	J	`jnl`	Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede
2012	—	`conf`	Design-for-test methodologies for current tests in Analog/Mixed-Signal Power SOCs. MWSCAS Kemal Kulovic, Samed Maltabas, Martin Margala
2012	B	`conf`	Evaluating FPGA-acceleration for real-time unstructured search. ISPASS Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede, Mitch Wright, Parthasarathy Ranganathan
2012	J	`jnl`	Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance. IEEE Trans. Very Large Scale Integr. Syst. Sohan Purohit, Martin Margala
2012	J	`jnl`	Novel Practical Built-in Current Sensors. J. Electron. Test. Samed Maltabas, Kemal Kulovic, Martin Margala
2012	J	`jnl`	Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application. Int. J. Reconfigurable Comput. Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Martin Margala
2012	J	`jnl`	Time-Based Embedded Test Instrument with Concurrent Voltage Measurement Capability. J. Electron. Test. Kemal Kulovic, Martin Margala
2011	—	`conf`	A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks. HPCS Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala
2011	—	`conf`	A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies. ECCTD Osman Kubilay Ekekon, Samed Maltabas, Martin Margala
2010	—	`conf`	A C++-embedded Domain-Specific Language for programming the MORA soft processor array. ASAP Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit
2010	B	`conf`	A new built-in IDDQ testing method using programmable BICS. ETS Samed Maltabas, Osman Kubilay Ekekon, Martin Margala
2010	C	`conf`	An area efficient design methodology for SEU tolerant digital circuits. ISCAS Sohan Purohit, David Harrington, Martin Margala
2010	J	`jnl`	Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. J. Low Power Electron. Sohan Purohit, Marco Lanuzza, Martin Margala
2010	—	`conf`	Design of self correcting radiation hardened digital circuits using decoupled ground bus. ACM Great Lakes Symposium on VLSI Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
2010	—	`conf`	Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform. ReConFig Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, Svein J. Knapskog
2010	—	`conf`	Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths. AHS Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
2010	C	`conf`	Novel programmable built-in current-sensor for analog, digital and mixed-signal circuits. ISCAS Osman Kubilay Ekekon, Samed Maltabas, Martin Margala
2010	—	`conf`	Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems. AHS Mohamed El-Hadedy, Sohan Purohit, Martin Margala, Svein J. Knapskog
2010	—	`conf`	Power minimization methodology for VCTL topologies. SoCC Osman Kubilay Ekekon, Samed Maltabas, Martin Margala, Ugur Çilingiroglu
2010	J	`jnl`	Radiation-Hardened Reconfigurable Array With Instruction Roll-Back. IEEE Embed. Syst. Lett. Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede
2010	C	`conf`	Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform. IAS Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, Svein J. Knapskog
2010	—	`conf`	Topology impact on the room temperature performance of THz-range ballistic deflection transistors. ACM Great Lakes Symposium on VLSI Vikas Kaushal, Ignacio Iñiguez-de-la-Torre, Martin Margala
2009	—	`conf`	A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic. ACM Great Lakes Symposium on VLSI Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
2009	B	`conf`	A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model. FPL Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala
2009	C	`conf`	Ballistic Deflection Transistors and the Emerging Nanoscale Era. ISCAS David Wolpert, Hiroshi Irie, Roman Sobolewski, Paul Ampadu, Quentin Diduck, Martin Margala
2009	J	`jnl`	Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electron. Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2009	Misc	`conf`	Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2009	—	`conf`	MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor. AHS Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede
2009	—	`conf`	New performance/power/area efficient, reliable full adder design. ACM Great Lakes Symposium on VLSI Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello
2009	—	`conf`	Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor. ERSA Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit
2009	—	`conf`	Study of leakage current mechanisms in ballistic deflection transistors. ACM Great Lakes Symposium on VLSI Vikas Kaushal, Quentin Diduck, Martin Margala
2009	—	`conf`	Varicap threshold logic. ACM Great Lakes Symposium on VLSI Samed Maltabas, Martin Margala, Ugur Çilingiroglu
2008	—	`conf`	A Digital BIST for Phase-Locked Loops. DFT Kevin Sliech, Martin Margala
2008	J	`jnl`	A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. John C. Liobe, Richard Geisler, Martin Margala
2008	C	`conf`	A portless SRAM Cell using stunted wordline drivers. ISCAS Michael Wieckowski, Martin Margala
2008	—	`conf`	Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2008	—	`conf`	Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. ReConFig Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello
2008	—	`conf`	Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. SoCC Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello
2007	—	`conf`	A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2007	J	`jnl`	A Processor-In-Memory Architecture for Multimedia Compression. IEEE Trans. Very Large Scale Integr. Syst. Brandon J. Jasionowski, Michelle K. Lay, Martin Margala
2007	C	`conf`	A Self-Biased Charge-Transfer Sense Amplifier. ISCAS Sandeep Patil, Michael Wieckowski, Martin Margala
2007	C	`conf`	Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test. IOLTS John C. Liobe, Martin Margala
2007	J	`jnl`	Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. John C. Liobe, Martin Margala
2007	J	`jnl`	Portless SRAM - A High-Performance Alternative to the 6T Methodology. IEEE J. Solid State Circuits Michael Wieckowski, Sandeep Patil, Martin Margala
2007	C	`conf`	Process and Temperature Calibration of PLLs with BiST Capabilities. ISCAS Richard Geisler, John C. Liobe, Martin Margala
2006	C	`conf`	A 2.4-GHz auto-calibration frequency synthesizer with on-chip built-in-self-test solution. ISCAS Sadeka Ali, Martin Margala
2006	C	`conf`	A versatile computation module for adaptable multimedia processors. ISCAS Yunan Xiang, R. Pettibon, Martin Margala
2006	—	`conf`	Adaptable Architectures for Signal Processing Applications. AHS Martin Margala
2006	C	`conf`	An integrated countermeasure against differential power analysis for secure smart-cards. ISCAS Pasquale Corsonello, Stefania Perri, Martin Margala
2006	J	`jnl`	Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
2006	—	`conf`	New Embedded Core Testing for System-on-Chips and System-in-Packages. CCECE Yuxin Wang, Martin Margala
2006	—	`conf`	On-Chip Integrated Antennas - The First Challenge for Reliable on-Chip Wireless Interconnects. CCECE Yuxin Wang, D. Makadia, Martin Margala
2006	C	`conf`	Process tolerant calibration circuit for PLL applications with BIST. ISCAS Quentin Diduck, John C. Liobe, Sadeka Ali, Martin Margala
2006	—	`conf`	Tutorial: RAM-based Circuits and Architectures for Multimedia and Signal Processing SOCs. SoCC Martin Margala
2005	—	`conf`	A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test. DFT Sadeka Ali, Gregory Briggs, Martin Margala
2005	—	`conf`	A New Test Methodology For DNL Error In Flash ADC's. DFT Michael Wieckowski, John C. Liobe, Quentin Diduck, Martin Margala
2005	J	`jnl`	A current based self-test methodology for RF front-end circuits. Microelectron. J. Anand Gopalan, Martin Margala, P. R. Mukund
2005	B	`conf`	A new SoC test architecture with RF/wireless connectivity. ETS Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
2005	—	`conf`	A novel five-transistor (5T) sram cell for high performance cache. SoCC Michael Wieckowski, Martin Margala
2005	A	`conf`	Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. ISLPED Marco Lanuzza, Martin Margala, Pasquale Corsonello
2005	J	`jnl`	Defect detection in analog and mixed circuits by neural networks using wavelet analysis. IEEE Trans. Reliab. Viera Stopjaková, Pavol Malosek, Marek Matej, Vladislav Nagy, Martin Margala
2005	J	`jnl`	Design of wireless on-wafer submicron characterization system. IEEE Trans. Very Large Scale Integr. Syst. Brian Moore, Martin Margala, Christopher J. Backhouse
2005	J	`jnl`	Efficient Addition Circuits for Modular Design of Processors-in-Memory. IEEE Trans. Circuits Syst. I Regul. Pap. Pasquale Corsonello, Stefania Perri, Martin Margala
2005	B	`conf`	Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. FPL Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello
2004	—	`conf`	6-bit low power low area frequency modulation based flash ADC. ISCAS (1) Quentin Diduck, Martin Margala
2004	—	`conf`	A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders. SoCC Michael Wieckowski, Martin Margala
2004	—	`conf`	A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time. ISCAS (4) Sadeka Ali, Martin Margala
2004	Misc	`conf`	A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems. VLSI Design Antonija Soldo, Anand Gopalan, P. R. Mukund, Martin Margala
2004	J	`jnl`	Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks. J. Electron. Test. Viera Stopjaková, Pavol Malosek, Daniel Micusík, Marek Matej, Martin Margala
2004	—	`conf`	Cost Model Analysis of DFT Based Fault Tolerant SOC Designs. ISQED Karthik Sundararaman, Shambhu J. Upadhyaya, Martin Margala
2004	Misc	`conf`	Design of Wireless Sub-Micron Characterization System. VTS Brian Moore, Christopher J. Backhouse, Martin Margala
2004	J	`jnl`	New approach to design for reusability of arithmetic cores in systems-on-chip. Integr. Martin Margala, Hongfan Wang
2004	—	`conf`	Sobel edge detection processor for a real-time volume rendering system. ISCAS (2) Natalia Kazakova, Martin Margala, Nelson G. Durdle
2003	C	`conf`	1-V ADPCM Processor for Low-Power Wireless Applications. VLSI-SOC Martin Margala, Magdy A. El-Moursy, Ali El-Moursy, Junmou Zhang, Wendi Beth Heinzelman
2003	C	`conf`	1.8V 0.18µm CMOS Novel Successive Approximation ADC. VLSI-SOC Martin Margala, Quentin Diduck, Eric Moule
2003	J	`jnl`	A versatile built-in CMOS sensing device for digital circuit parametric test. IEEE Trans. Instrum. Meas. Marco S. Dragic, Martin Margala
2003	—	`conf`	Control Constrained Resource Partitioning for Complex SoCs. DFT Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
2003	C	`conf`	Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters. VLSI-SOC Martin Margala, John C. Liobe, Quentin Diduck
2003	—	`conf`	Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits. DFT Marco S. Dragic, Martin Margala
2002	—	`conf`	A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test. ISVLSI Srdjan Dragic, Martin Margala
2002	—	`conf`	Application-specific low-voltage current amplifier for system-on-chip I ICECS Srdjan Dragic, Martin Margala
2002	—	`conf`	Low-voltage analog current detector supporting at-speed BIST. ISCAS (1) Srdjan Dragic, Igor M. Filanovsky, Martin Margala
2002	—	`conf`	Minimizing concurrent test time in SoC's by balancing resource usage. ACM Great Lakes Symposium on VLSI Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
2002	—	`conf`	Neural Networks-Based Parametric Testing of Analog IC. DFT Viera Stopjaková, Daniel Micusík, Lubica Benusková, Martin Margala
2002	—	`conf`	Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor. ACM Great Lakes Symposium on VLSI Rong Lin, Martin Margala
2001	—	`conf`	A novel wide-band CMOS current amplifying cell and its application in power supply current monitoring. ICECS Srdjan Dragic, Igor M. Filanovsky, Martin Margala
2001	—	`conf`	Fast and low-power inner product processor. ISCAS (4) Natalia Kazakova, Raymond J. Sung, Nelson G. Durdle, Martin Margala, Julien Lamoureux
2001	C	`conf`	Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. VLSI-SOC Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi
2000	—	`conf`	I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test. IOLTW Martin Margala, Srdjan Dragic, Ahmed El-Abasiry, Samuel Ekpe, Viera Stopjaková
2000	C	`conf`	Optimization techniques for maximum power-efficiency of deep sub-micron CMOS digital circuits. ISCAS Daniel S. C. Kwok, Martin Margala
1999	—	`conf`	Low Power SRAMs for Battery Operation. MTDT Martin Margala
1999	—	`ch.`	Low-Power Memory Circuits. The VLSI Handbook Martin Margala
1999	—	`conf`	Low-Power SRAM Circuit Design. MTDT Martin Margala
1998	J	`jnl`	Noncomplementary BiCMOS logic and CMOS logic for low-voltage, low-power operation-a comparative study. IEEE J. Solid State Circuits Martin Margala, Nelson G. Durdle
1995	J	`jnl`	A 33 MHz 16-bit gradient calculator for real-time volume imaging. Comput. Graph. Martin Margala, Nelson G. Durdle, Scott Juskiw, V. James Raso, Doug L. Hill
1994	—	`conf`	A 33MHz 16. Bit Gradient Calculator for Real-Time Volume Imaging. Workshop on Graphics Hardware Martin Margala, Nelson G. Durdle, V. James Raso, Doug L. Hill