Martin Kumm - RankMe

72 papers A 1B 9C 13Misc 2Journal 28Unranked 18

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Continuous-Flow Data-Rate-Aware CNN Inference on FPGA. CoRR Tobias Habermann, Michael Mecik, Zhenyu Wang, César David Vera, Martin Kumm, Mario Garrido
2026	J	`jnl`	Data-Rate-Aware High-Speed CNN Inference on FPGAs. CoRR Tobias Habermann, Martin Kumm
2025	—	`conf`	Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators. IEEECONF Michael Mecik, Martin Kumm
2025	J	`jnl`	Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators. CoRR Michael Mecik, Martin Kumm
2025	J	`jnl`	Multi-Resolution Remote Sensing Dataset for the Detection of Anthropogenic Litter: A Multi-Platform and Multi-Sensor Approach. Data Robert Rettig, Felix Becker, Alexander Berghoff, Tobias Binkele, Wolfram Michael Butter, Tilman Floehr, Martin Kumm, Carolin Leluschko, Florian Littau, Elmar Reinders, Eike Rodenbäck, Tobias Schmid, Sabine Schründer, Sören Schweigert, Michael Sinhuber, Jens Wellhausen, Frederic T. Stahl, Christoph Tholen
2024	J	`jnl`	Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability. IEEE Trans. Circuits Syst. I Regul. Pap. Nicolai Fiege, Martin Kumm, Peter Zipf
2024	—	`conf`	Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs. ASAP Andreas Böttcher, Martin Kumm
2024	J	`jnl`	Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs. CoRR Andreas Böttcher, Martin Kumm
2024	C	`conf`	Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs. ARITH Andreas Böttcher, Martin Kumm
2024	J	`jnl`	Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs. CoRR Andreas Böttcher, Martin Kumm
2023	J	`jnl`	Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Martin Kumm, Anastasia Volkova, Silviu-Ioan Filip
2023	Misc	`conf`	Hardware-Optimal Digital FIR Filters: One ILP to Rule Them all and in Faithfulness Bind Them. ACSSC Anastasia Volkova, Rémi Garcia, Florent de Dinechin, Martin Kumm
2023	C	`conf`	More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers. ISCAS Martin Hardieck, Tobias Habermann, Fabian Wagner, Michael Mecik, Martin Kumm, Peter Zipf
2023	J	`jnl`	Towards Globally Optimal Design of Multipliers for FPGAs. IEEE Trans. Computers Andreas Böttcher, Martin Kumm
2022	J	`jnl`	Hardware-Aware Design of Multiplierless Second-Order IIR Filters With Minimum Adders. IEEE Trans. Signal Process. Rémi Garcia, Anastasia Volkova, Martin Kumm, Alexandre Goldsztejn, Jonas Kühle
2022	—	`conf`	Hardware-Aware Quantization for Multiplierless Neural Network Controllers. APCCAS Tobias Habermann, Jonas Kühle, Martin Kumm, Anastasia Volkova
2022	B	`conf`	Resource Optimal Squarers for FPGAs. FPL Andreas Böttcher, Martin Kumm, Florent de Dinechin
2022	C	`conf`	Truncated Multiple Constant Multiplication with Minimal Number of Full Adders. ISCAS Rémi Garcia, Anastasia Volkova, Martin Kumm
2021	J	`jnl`	Hardware-aware Design of Multiplierless Second-Order IIR Filters with Minimum Adders. CoRR Rémi Garcia, Anastasia Volkova, Martin Kumm, Alexandre Goldsztejn, Jonas Kühle
2021	C	`conf`	Resource Optimal Truncated Multipliers for FPGAs. ARITH Andreas Böttcher, Martin Kumm, Florent de Dinechin
2021	C	`conf`	Towards Arithmetic-Centered Filter Design. ARITH Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Anastasia Volkova
2020	J	`jnl`	AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. IEEE Trans. Very Large Scale Integr. Syst. Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong
2020	Misc	`conf`	Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs. FCCM Lukas Sommer, Lukas Weber, Martin Kumm, Andreas Koch
2020	C	`conf`	Heuristics for the Design of Large Multipliers for FPGAs. ARITH Andreas Böttcher, Keanu Kullmann, Martin Kumm
2020	—	`conf`	Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design. ASP-DAC Patrick Sittel, John Wickerson, Martin Kumm, Peter Zipf
2019	J	`jnl`	AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. CoRR Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong
2019	—	`conf`	Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. Euro-Par Julian Oppermann, Patrick Sittel, Martin Kumm, Melanie Reuter-Oppermann, Andreas Koch, Oliver Sinnen
2019	—	`conf`	Efficient Error-Tolerant Quantized Neural Network Accelerators. DFT Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
2019	J	`jnl`	Efficient Error-Tolerant Quantized Neural Network Accelerators. CoRR Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
2019	—	`conf`	Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. ReConFig Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf
2019	A	`conf`	Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. FPGA Martin Hardieck, Martin Kumm, Konrad Möller, Peter Zipf
2019	C	`conf`	Table-Based versus Shift-And-Add Constant Multipliers for FPGAs. ARITH Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Luc Forget
2019	J	`jnl`	Unrolling Ternary Neural Networks. CoRR Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong
2019	J	`jnl`	Unrolling Ternary Neural Networks. ACM Trans. Reconfigurable Technol. Syst. Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong
2019	J	`jnl`	World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s. IEEE Trans. Circuits Syst. I Regul. Pap. Mario Garrido, Konrad Möller, Martin Kumm
2018	J	`jnl`	Advanced Compressor Tree Synthesis for FPGAs. IEEE Trans. Computers Martin Kumm, Johannes Kappauf
2018	—	`conf`	Constant Matrix Multiplication with Ternary Adders. ICECS Martin Hardieck, Martin Kumm, Patrick Sittel, Peter Zipf
2018	B	`conf`	ILP-Based Modulo Scheduling and Binding for Register Minimization. FPL Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch
2018	C	`conf`	Karatsuba with Rectangular Multipliers for FPGAs. ARITH Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, Peter Zipf
2018	J	`jnl`	Optimal Constant Multiplication Using Integer Linear Programming. IEEE Trans. Circuits Syst. II Express Briefs Martin Kumm
2018	J	`jnl`	Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Konrad Möller, Martin Kumm, Mario Garrido, Peter Zipf
2018	J	`jnl`	Optimal Single Constant Multiplication Using Ternary Adders. IEEE Trans. Circuits Syst. II Express Briefs Martin Kumm, Oscar Gustafsson, Mario Garrido, Peter Zipf
2018	—	`conf`	ScaLP: A Light-Weighted (MI)LP-Library. MBMV Patrick Sittel, Thomas Schönwälder, Martin Kumm, Peter Zipf
2017	—	`conf`	High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. MBMV Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf
2017	—	`conf`	Model-based hardware design based on compatible sets of isomorphic subgraphs. FPT Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca, Mark Jervis
2017	J	`jnl`	Optimization of Constant Matrix Multiplication with Low Power and High Throughput. IEEE Trans. Computers Martin Kumm, Martin Hardieck, Peter Zipf
2017	J	`jnl`	Reconfigurable Constant Multiplication for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf
2017	C	`conf`	Resource Optimal Design of Large Multipliers for FPGAs. ARITH Martin Kumm, Johannes Kappauf, Matei Istoan, Peter Zipf
2016	J	`jnl`	CORDIC II: A New Improved CORDIC Algorithm. IEEE Trans. Circuits Syst. II Express Briefs Mario Garrido, Petter Kallstrom, Martin Kumm, Oscar Gustafsson
2016	J	`jnl`	Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs". Int. J. Reconfigurable Comput. Martin Kumm, Peter Zipf
2016	B	`conf`	Efficient sum of absolute difference computation on FPGAs. FPL Martin Kumm, Marco Kleinlein, Peter Zipf
2016	—	`—`	Multiple constant multiplication optimizations for field programmable gate arrays. Martin Kumm
2015	C	`conf`	An Efficient Softcore Multiplier Architecture for Xilinx FPGAs. ARITH Martin Kumm, Shahid Abbas, Peter Zipf
2015	—	`conf`	Efficient structural adder pipelining in transposed form FIR filters. DSP Mathias Faust, Martin Kumm, Chip-Hong Chang, Peter Zipf
2015	J	`jnl`	Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits. CoRR Konrad Möller, Martin Kumm, Charles-Frederic Müller, Peter Zipf
2014	—	`conf`	Dynamically Reconfigurable Constant Multiplication on FPGAs. MBMV Konrad Möller, Martin Kumm, Björn Barschtipan, Peter Zipf
2014	—	`conf`	Efficient High Speed Compression Trees on Xilinx FPGAs. MBMV Martin Kumm, Peter Zipf
2014	B	`conf`	Pipelined compressor tree optimization using integer linear programming. FPL Martin Kumm, Peter Zipf
2014	B	`conf`	Pipelined reconfigurable multiplication with constants on FPGAs. FPL Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf
2013	—	`conf`	Dynamically reconfigurable FIR filter architectures with fast reconfiguration. ReCoSoC Martin Kumm, Konrad Möller, Peter Zipf
2013	J	`jnl`	FIR filter optimization for video processing on FPGAs. EURASIP J. Adv. Signal Process. Martin Kumm, Diana Fanghänel, Konrad Möller, Peter Zipf, Uwe Meyer-Baese
2013	B	`conf`	Multiple constant multiplication with ternary adders. FPL Martin Kumm, Martin Hardieck, Jens Willkomm, Peter Zipf, Uwe Meyer-Baese
2013	C	`conf`	Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs. ISCAS Martin Kumm, Konrad Möller, Peter Zipf
2013	C	`conf`	Reconfigurable FIR filter using distributed arithmetic on FPGAs. ISCAS Martin Kumm, Konrad Möller, Peter Zipf
2012	B	`conf`	Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system. FPL Michael Kunz, Martin Kumm, Martin Heide, Peter Zipf
2012	—	`conf`	Hybrid multiple constant multiplication for FPGAs. ICECS Martin Kumm, Peter Zipf
2012	C	`conf`	Pipelined adder graph optimization for high speed multiple constant multiplication. ISCAS Martin Kumm, Peter Zipf, Mathias Faust, Chip-Hong Chang
2012	B	`conf`	Reduced complexity single and multiple constant multiplication in floating point precision. FPL Martin Kumm, Katharina Liebisch, Peter Zipf
2011	—	`conf`	High speed low complexity FPGA-based FIR filters using pipelined adder graphs. FPT Martin Kumm, Peter Zipf
2010	J	`jnl`	An FPGA-Based Linear All-Digital Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. Martin Kumm, Harald Klingbeil, Peter Zipf
2008	B	`conf`	Digital hilbert transformers for FPGA-based phase-locked loops. FPL Martin Kumm, M. Shahab Sanjari
2006	—	`conf`	Implementation of Realtime and Highspeed Phase Detector on FPGA. ARC Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner