Martin Kinyua

14 papers Journal 10Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 700 MS/s 12-bit Pipeline-ADC With a Sub-Range 6-bit Back-End Achieving 79 dB Signal-to-Distortion Ratio and FoM of 170.1 dB Near Nyquist Frequency.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shangfeng Qiu, Amr W. Hassan, Martin Kinyua, Eric G. Soenen, Jose Silva-Martinez
2024 J jnl
Look-Up Table-Based Digital Calibration for the Correction of Pipeline Analog-to-Digital Converter Non-Idealities.
IEEE Access
Shangfeng Qiu, Dadian Zhou, Martin Kinyua, Jose Silva-Martinez
2020 J jnl
A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator.
IEEE J. Solid State Circuits
Dadian Zhou, Junning Jiang, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
2020 — conf
A 72.6 dB SNDR 14b 100 MSPS Ring Amplifier Based Pipelined SAR ADC with Dynamic Deadzone Control in 16 nm CMOS.
CICC
Martin Kinyua, Eric G. Soenen
2019 J jnl
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dadian Zhou, Carlos Briseno-Vidrios, Junning Jiang, Chulhyun Park, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
2019 J jnl
A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohammad H. Naderi, Chulhyun Park, Suraj Prakash, Martin Kinyua, Eric G. Soenen, José Silva-Martínez
2018 J jnl
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs.
IEEE J. Solid State Circuits
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
2017 J jnl
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS.
IEEE J. Solid State Circuits
Alexander Edward, Qiyuan Liu, Carlos Briseno-Vidrios, Martin Kinyua, Eric G. Soenen, Aydin Ilker Karsilayan, José Silva-Martínez
2017 J jnl
A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques.
IEEE J. Solid State Circuits
Qiyuan Liu, Alexander Edward, Martin Kinyua, Eric G. Soenen, José Silva-Martínez
2015 J jnl
Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Amplifier With Global Feedback and Digital Control in 55 nm CMOS.
IEEE J. Solid State Circuits
Martin Kinyua, Ruopeng Wang, Eric G. Soenen
2014 — conf
A 105dBA SNR, 0.0031% THD+N filterless class-D amplifier with discrete time feedback control in 55nm CMOS.
CICC
Martin Kinyua, Ruopeng Wang, Eric G. Soenen
2012 J jnl
Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS.
IEEE J. Solid State Circuits
Justin Shi, Eric G. Soenen, Alan Roth, Ying-Chih Hsu, Martin Kinyua
2010 — conf
A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS.
ISSCC
Eric G. Soenen, Alan Roth, Justin Shi, Martin Kinyua, Justin Gaither, Elizabeth Ortynska
2004 — conf
Digital background auto-calibration of DAC non-linearity in pipelined ADCs.
ISCAS (1)
Martin Kinyua, Franco Maloberti, William Gosney