Martin D. F. Wong

323 papers A* 44A 58B 4C 6Misc 2Journal 115Unranked 87
YearRankTypeTitle / Venue / Authors
2026 — conf
CausalTuner: Will Causality Help High-Dimensional EDA Tool Parameter Tuning.
ASP-DAC
Ziyang Yu, Peng Xu, Su Zheng, Siyuan Xu, Hao Geng, Bei Yu, Martin D. F. Wong
2026 — conf
Gradient-Guided RC Weighting for Timing-Driven Global Routing.
ISPD
Liang Xiao, Qinkai Duan, Leilei Jin, Jinwei Liu, Tsung-Yi Ho, Evangeline F. Y. Young, Martin D. F. Wong
2026 J jnl
MALT: ML Assisted Shallow-Light Tree Construction.
ACM Trans. Design Autom. Electr. Syst.
Liang Xiao, Jinwei Liu, Lixin Liu, Qijing Wang, Evangeline F. Y. Young, Martin D. F. Wong
2026 J jnl
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
ACM Trans. Design Autom. Electr. Syst.
Siting Liu, Jieya Zhou, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong
2025 J jnl
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling.
ACM Trans. Design Autom. Electr. Syst.
Binwu Zhu, Su Zheng, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2025 A* conf
Curvilinear Optical Proximity Correction via Cardinal Spline.
DAC
Su Zheng, Xiaoxiao Liang, Ziyang Yu, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2025 — conf
Dr. Guide: AI-Guided Detailed Routing.
MLCAD
Qijing Wang, Wing Ho Lau, Tsung-Yi Ho, Evangeline F. Y. Young, Martin D. F. Wong
2025 A conf
Fast Dynamic IR-Drop Prediction with Dual-Path Spatial-Temporal Attention.
DATE
Bangqi Fu, Lixin Liu, Qijing Wang, Yutao Wang, Martin D. F. Wong, Evangeline F. Y. Young
2025 J jnl
Hierarchical Partitioning-Based Interchip Redistribution Layer Routing for Fan-Out Wafer-Level Packaging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haoyang Xu, Xing Huang, Zhen Zhuang, Zhiwen Yu, Bin Guo, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong
2025 J jnl
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lancheng Zou, Su Zheng, Peng Xu, Siting Liu, Bei Yu, Martin D. F. Wong
2025 — conf
ML-Based Fine-Grained Modeling of DC Current Crowding in Power Delivery TSVs for Face-to-Face 3D ICs.
ISPD
Zheng Yang, Zhen Zhuang, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong, Sung Kyu Lim
2025 — conf
POAgent: A Multi-agent Controller Towards Adaptive Parameter Optimization.
KSEM (1)
Qijing Wang, Martin D. F. Wong, Evangeline F. Y. Young
2025 J jnl
RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyang Yu, Su Zheng, Wenqian Zhao, Shuo Yin, Xiaoxiao Liang, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2025 A* conf
SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation.
DAC
Ziyang Yu, Peng Xu, Zixiao Wang, Binwu Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Bei Yu, Martin D. F. Wong
2025 J jnl
Sign-Off Timing Considerations via Concurrent Routing Topology Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2025 J jnl
Streamlining Computational Lithography With Efficient Pattern Database.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Su Zheng, Wenqian Zhao, Shuyuan Sun, Fan Yang, Bei Yu, Martin D. F. Wong
2025 B conf
TRPlaceFPGA-MP: A Two-Stage Reinforcement Learning Framework for Fast FPGA Macro Placer.
FPL
Qin Luo, Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong
2024 — conf
A Multi-agent Generative Model for Collaborative Global Routing Refinement.
ACM Great Lakes Symposium on VLSI
Qijing Wang, Jinwei Liu, Martin D. F. Wong, Evangeline F. Y. Young
2024 Misc conf
A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints.
FCCM
Qin Luo, Xinshi Zang, Qijing Wang, Fangzhou Wang, Evangeline F. Y. Young, Martin D. F. Wong
2024 J jnl
AdaOPC 2.0: Enhanced Adaptive Mask Optimization Framework for via Layers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wenqian Zhao, Xufeng Yao, Shuo Yin, Yang Bai, Ziyang Yu, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2024 J jnl
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration.
ACM Trans. Design Autom. Electr. Syst.
Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2024 B conf
CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs.
ASPDAC
Bangqi Fu, Lixin Liu, Yang Sun, Wing Ho Lau, Martin D. F. Wong, Evangeline F. Y. Young
2024 — conf
ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation.
ACM Great Lakes Symposium on VLSI
Qijing Wang, Xiaopeng Zhang, Martin D. F. Wong, Evangeline F. Y. Young
2024 — conf
Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing.
ACM Great Lakes Symposium on VLSI
Xinshi Zang, Qin Luo, Zhongwei Shao, Jifeng Zhang, Evangeline F. Y. Young, Martin D. F. Wong
2024 A* conf
EMOGen: Enhancing Mask Optimization via Pattern Generation.
DAC
Su Zheng, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2024 A* conf
GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis.
DAC
Shiju Lin, Guannan Guo, Tsung-Wei Huang, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong
2024 A conf
Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration.
ICCAD
Bangqi Fu, Lixin Liu, Martin D. F. Wong, Evangeline F. Y. Young
2024 — conf
ISPD 2024 Lifetime Achievement Award Bio.
ISPD
Martin D. F. Wong
2024 A* conf
Improving Neural ODE Training with Temporal Adaptive Batch Normalization.
NeurIPS
Su Zheng, Zhengqi Gao, Fan-Keng Sun, Duane S. Boning, Bei Yu, Martin D. F. Wong
2024 J jnl
L2O-ILT: Learning to Optimize Inverse Lithography Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Binwu Zhu, Su Zheng, Ziyang Yu, Guojin Chen, Yuzhe Ma, Fan Yang, Bei Yu, Martin D. F. Wong
2024 A* conf
Massively Parallel AIG Resubstitution.
DAC
Yang Sun, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young
2024 — conf
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
ISPD
Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong
2024 A* conf
Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning.
AAAI
Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2024 J jnl
Ultrafast Source Mask Optimization via Conditional Discrete Diffusion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guojin Chen, Zixiao Wang, Bei Yu, David Z. Pan, Martin D. F. Wong
2024 J jnl
Xplace: An Extremely Fast and Extensible Placement Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lixin Liu, Bangqi Fu, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong
2023 J jnl
A GPU-Accelerated Framework for Path-Based Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guannan Guo, Tsung-Wei Huang, Yibo Lin, Zizheng Guo, Sushma Yellapragada, Martin D. F. Wong
2023 J jnl
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU.
CoRR
Wenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu, Martin D. F. Wong
2023 J jnl
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wenqian Zhao, Yang Bai, Qi Sun, Wenbo Li, Haisheng Zheng, Nianjuan Jiang, Jiangbo Lu, Bei Yu, Martin D. F. Wong
2023 J jnl
AdaOPC: A Self-Adaptive Mask Optimization Framework For Real Design Patterns.
CoRR
Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2023 J jnl
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization.
ACM Trans. Design Autom. Electr. Syst.
Su Zheng, Hao Geng, Chen Bai, Bei Yu, Martin D. F. Wong
2023 — conf
CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems.
ACM Great Lakes Symposium on VLSI
Xinshi Zang, Lei Chen, Xing Li, Wilson W. K. Thong, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong
2023 J jnl
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyang Yu, Peiyu Liao, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2023 A* conf
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement.
DAC
Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 J jnl
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction.
ACM Trans. Design Autom. Electr. Syst.
Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 J jnl
Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bentian Jiang, Xinshi Zang, Martin D. F. Wong, Evangeline F. Y. Young
2023 A conf
Fast STA Graph Partitioning Framework for Multi-GPU Acceleration.
DATE
Guannan Guo, Tsung-Wei Huang, Martin D. F. Wong
2023 J jnl
GAMER: GPU-Accelerated Maze Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shiju Lin, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong
2023 A conf
IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration.
ICCAD
Ziyang Yu, Chen Bai, Shoubo Hu, Ran Chen, Taohai He, Mingxuan Yuan, Bei Yu, Martin D. F. Wong
2023 A conf
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction.
ICCAD
Su Zheng, Lancheng Zou, Peng Xu, Siting Liu, Bei Yu, Martin D. F. Wong
2023 A* conf
LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing.
NeurIPS
Su Zheng, Haoyu Yang, Binwu Zhu, Bei Yu, Martin D. F. Wong
2023 A* conf
Mitigating Distribution Shift for Congestion Optimization in Global Placement.
DAC
Su Zheng, Lancheng Zou, Siting Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 A conf
Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding.
ICCAD
Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong
2023 A* conf
On a Moreau Envelope Wirelength Model for Analytical Global Placement.
DAC
Peiyu Liao, Hongduo Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 — conf
OpenILT: An Open Source Inverse Lithography Technique Framework (Invited Paper).
ASICON
Su Zheng, Bei Yu, Martin D. F. Wong
2023 A* conf
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields.
DAC
Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2023 J jnl
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields.
CoRR
Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2023 — conf
SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems.
ACM Great Lakes Symposium on VLSI
Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong
2022 A* conf
A2-ILT: GPU accelerated ILT with spatial attention mechanism.
DAC
Qijing Wang, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young
2022 A conf
ATLAS: A Two-Level Layer-Aware Scheme for Routing with Cell Movement.
ICCAD
Xinshi Zang, Fangzhou Wang, Jinwei Liu, Martin D. F. Wong
2022 A conf
AdaOPC: A Self-Adaptive Mask Optimization Framework for Real Design Patterns.
ICCAD
Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2022 — conf
Efficient Design Rule Checking Script Generation via Key Information Extraction.
MLCAD
Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong
2022 — ch.
High-Level Synthesis for Minimizing Power Side-Channel Information Leakage.
Behavioral Synthesis for Hardware Security
S. T. Choden Konigsmark, Wei Ren, Martin D. F. Wong, Deming Chen
2022 A* conf
NovelRewrite: node-level parallel AIG rewriting.
DAC
Shiju Lin, Jinwei Liu, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young
2022 A* conf
Partition and place finite element model on wafer-scale engine.
DAC
Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young
2022 A conf
Superfast Full-Scale CPU-Accelerated Global Routing.
ICCAD
Shiju Lin, Martin D. F. Wong
2022 A conf
WaferHSL: Wafer Failure Pattern Classification with Efficient Human-Like Staged Learning.
ICCAD
Qijing Wang, Martin D. F. Wong
2022 A* conf
Xplace: an extremely fast and extensible global placement framework.
DAC
Lixin Liu, Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young
2021 A conf
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU.
ICCAD
Wenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu, Martin D. F. Wong
2021 A conf
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework.
ICCAD
Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2021 J jnl
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsung-Wei Huang, Yibo Lin, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong
2021 A conf
GAMER: GPU Accelerated Maze Routing.
ICCAD
Shiju Lin, Jinwei Liu, Martin D. F. Wong
2021 A conf
GPU-accelerated Critical Path Generation with Path Constraints.
ICCAD
Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong
2021 A* conf
GPU-accelerated Path-based Timing Analysis.
DAC
Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong
2021 A conf
Hotspot Detection via Multi-task Learning and Transformer Encoder.
ICCAD
Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu, Martin D. F. Wong
2021 J jnl
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsung-Wei Huang, Guannan Guo, Chun-Xun Lin, Martin D. F. Wong
2021 J jnl
OpenTimer v2: A Parallel Incremental Timing Analysis Engine.
IEEE Des. Test
Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong
2021 A conf
Starfish: An Efficient P&R Co-Optimization Engine with A*-based Partial Rerouting.
ICCAD
Fangzhou Wang, Lixin Liu, Jingsong Chen, Jinwei Liu, Xinshi Zang, Martin D. F. Wong
2021 A conf
TopoPart: a Multi-level Topology-Driven Partitioning Framework for Multi-FPGA Systems.
ICCAD
Dan Zheng, Xinshi Zang, Martin D. F. Wong
2020 A* conf
An Efficient Critical Path Generation Algorithm Considering Extensive Path Constraints.
DAC
Guannan Guo, Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong
2020 B conf
An Efficient Work-Stealing Scheduler for Task Dependency Graph.
ICPADS
Chun-Xun Lin, Tsung-Wei Huang, Martin D. F. Wong
2020 C conf
Learn to Floorplan through Acquisition of Effective Local Search Heuristics.
ICCD
Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, Martin D. F. Wong
2020 J jnl
On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Daifeng Guo, Hongbo Zhang, Martin D. F. Wong
2019 A* conf
A Modern C++ Parallel Task Programming Library.
ACM Multimedia
Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong
2019 — conf
An Efficient and Composable Parallel Task Programming Library.
HPEC
Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong
2019 A conf
Cpp-Taskflow: Fast Task-Based Parallel Programming Using Modern C++.
IPDPS
Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong
2019 A* conf
Distributed Timing Analysis at Scale.
DAC
Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong
2019 J jnl
DtCraft: A High-Performance Distributed Execution Engine at Scale.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong
2019 A* conf
Essential Building Blocks for Creating an Open-source EDA Project.
DAC
Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong
2018 — conf
A Distributed Power Grid Analysis Framework from Sequential Stream Graph.
ACM Great Lakes Symposium on VLSI
Chun-Xun Lin, Tsung-Wei Huang, Ting Yu, Martin D. F. Wong
2018 A* conf
A General-purpose Distributed Programming System using Data-parallel Streams.
ACM Multimedia
Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong
2018 — conf
A highly compressed timing macro-modeling algorithm for hierarchical and incremental timing analysis.
ASP-DAC
Tin-Yin Lai, Martin D. F. Wong
2018 A conf
Accelerate analytical placement with GPU: A generic approach.
DATE
Chun-Xun Lin, Martin D. F. Wong
2018 — conf
Accurate Models for Optimizing Tapered Microchannel Heat Sinks in 3D ICs.
ISVLSI
Leslie Hwang, Beomjin Kwon, Martin D. F. Wong
2018 — conf
MtDetector: A High-performance Marine Traffic Detector at Stream Scale.
DEBS
Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong
2018 — conf
On coloring rectangular and diagonal grid graphs for multiple patterning lithography.
ASP-DAC
Daifeng Guo, Hongbo Zhang, Martin D. F. Wong
2018 — conf
Routing at compile time.
ISQED
Chun-Xun Lin, Tsung-Wei Huang, Martin D. F. Wong
2017 A conf
DtCraft: A distributed execution engine for compute-intensive applications.
ICCAD
Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong
2017 — conf
High-Level Synthesis for side-channel defense.
ASAP
S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong
2017 A* conf
LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs.
DAC
Tin-Yin Lai, Tsung-Wei Huang, Martin D. F. Wong
2016 A* conf
A distributed timing analysis framework for large designs.
DAC
Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran
2016 — ch.
Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach.
Encyclopedia of Algorithms
Martin D. F. Wong, Hannah Honghua Yang
2016 — conf
Contact layer decomposition to enable DSA with multi-patterning technique for standard cell based layout.
ASP-DAC
Zigang Xiao, Chun-Xun Lin, Martin D. F. Wong, Hongbo Zhang
2016 — conf
Early Days of Automatic Floorplan Design.
ISPD
Martin D. F. Wong
2016 A* conf
Information dispersion for trojan defense through high-level synthesis.
DAC
S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong
2016 — ch.
Layout Decomposition for Multiple Patterning.
Encyclopedia of Algorithms
Haitong Tian, Martin D. F. Wong
2016 — conf
Performance evaluation considering mask misalignment in multiple patterning decomposition.
ISQED
Haitong Tian, Martin D. F. Wong
2016 J jnl
PolyPUF: Physically Secure Self-Divergence.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sven Tenzing Choden Konigsmark, Deming Chen, Martin D. F. Wong
2016 J jnl
UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPR.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsung-Wei Huang, Martin D. F. Wong
2015 — conf
Accelerated Path-Based Timing Analysis with MapReduce.
ISPD
Tsung-Wei Huang, Martin D. F. Wong
2015 J jnl
Accelerating aerial image simulation using improved CPU/GPU collaborative computing.
Comput. Electr. Eng.
Fan Zhang, Chen Hu, Pei-Ci Wu, Hongbo Zhang, Martin D. F. Wong
2015 — conf
An efficient linear time triple patterning solver.
ASP-DAC
Haitong Tian, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong
2015 — conf
Contact pitch and location prediction for Directed Self-Assembly template verification.
ASP-DAC
Zigang Xiao, Yuelin Du, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang
2015 — conf
Early Days of Circuit Placement.
ISPD
Martin D. F. Wong
2015 A* conf
Layout optimization and template pattern verification for directed self-assembly (DSA).
DAC
Zigang Xiao, Daifeng Guo, Martin D. F. Wong, He Yi, Maryann C. Tung, H.-S. Philip Wong
2015 — conf
On fast timing closure: speeding up incremental path-based timing analysis with mapreduce.
SLIP
Tsung-Wei Huang, Martin D. F. Wong
2015 A conf
OpenTimer: A High-Performance Timing Analysis Tool.
ICCAD
Tsung-Wei Huang, Martin D. F. Wong
2015 — conf
Polynomial time optimal algorithm for stencil row planning in e-beam lithography.
ASP-DAC
Daifeng Guo, Yuelin Du, Martin D. F. Wong
2014 — conf
CNPUF: A Carbon Nanotube-based Physically Unclonable Function for secure low-energy hardware design.
ASP-DAC
S. T. Choden Konigsmark, Leslie Hwang, Deming Chen, Martin D. F. Wong
2014 A* conf
Directed Self-Assembly (DSA) Template Pattern Verification.
DAC
Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang
2014 — conf
Efficient simulation-based optimization of power grid with on-chip voltage regulator.
ASP-DAC
Ting Yu, Martin D. F. Wong
2014 A conf
Fast path-based timing analysis for CPPR.
ICCAD
Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong
2014 A* conf
On Timing Closure: Buffer Insertion for Hold-Violation Removal.
DAC
Pei-Ci Wu, Martin D. F. Wong, Ivailo Nedelchev, Sarvesh Bhardwaj, Vidyamani Parkhe
2014 A conf
Optimization of standard cell based detailed placement for 16 nm FinFET process.
DATE
Yuelin Du, Martin D. F. Wong
2014 Misc conf
System-of-PUFs: Multilevel security for embedded systems.
CODES+ISSS
S. T. Choden Konigsmark, Leslie K. Hwang, Deming Chen, Martin D. F. Wong
2014 A conf
Triple patterning aware detailed placement with constrained pattern assignment.
ICCAD
Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong
2014 — conf
UI-route: An ultra-fast incremental maze routing algorithm.
SLIP
Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong
2014 A conf
UI-timer: an ultra-fast clock network pessimism removal algorithm.
ICCAD
Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong
2013 J jnl
A Polynomial Time Exact Algorithm for Overlay-Resistant Self-Aligned Double Patterning (SADP) Layout Decomposition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zigang Xiao, Yuelin Du, Hongbo Zhang, Martin D. F. Wong
2013 — conf
A novel and efficient method for power pad placement optimization.
ISQED
Ting Yu, Martin D. F. Wong
2013 J jnl
A routing algorithm for graphene nanoribbon circuit.
ACM Trans. Design Autom. Electr. Syst.
Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong, Deming Chen
2013 — conf
Advances in wire routing.
ISQED
Martin D. F. Wong
2013 — conf
An ILP-based automatic bus planner for dense PCBs.
ASP-DAC
Pei-Ci Wu, Qiang Ma, Martin D. F. Wong
2013 A conf
Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library.
ICCAD
Yuelin Du, Daifeng Guo, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang, Qiang Ma
2013 A conf
Constrained pattern assignment for standard cell based triple patterning lithography.
ICCAD
Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong
2013 A conf
Efficient aerial image simulation on multi-core SIMD CPU.
ICCAD
Pei-Ci Wu, Tan Yan, Hongbo Zhang, Martin D. F. Wong
2013 — conf
Linear time algorithm to find all relocation positions for EUV defect mitigation.
ASP-DAC
Yuelin Du, Hongbo Zhang, Qiang Ma, Martin D. F. Wong
2013 — conf
Network flow modeling for escape routing on staggered pin arrays.
ASP-DAC
Pei-Ci Wu, Martin D. F. Wong
2013 A conf
Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time.
ICCAD
Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong
2013 A* conf
Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography.
DAC
Yuelin Du, Qiang Ma, Hua Song, James P. Shiely, Gerard Luk-Pat, Alexander Miloslavsky, Martin D. F. Wong
2013 C conf
The nature of optimization problem challenges in physical synthesis.
ACC
Ismail Bustany, Igor L. Markov, Martin D. F. Wong
2012 J jnl
A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng
2012 — conf
A polynomial time exact algorithm for self-aligned double patterning layout decomposition.
ISPD
Zigang Xiao, Yuelin Du, Hongbo Zhang, Martin D. F. Wong
2012 A conf
A polynomial time triple patterning algorithm for cell based row-structure layout.
ICCAD
Haitong Tian, Hongbo Zhang, Qiang Ma, Zigang Xiao, Martin D. F. Wong
2012 J jnl
Advances in PCB Routing.
Inf. Media Technol.
Tan Yan, Qiang Ma, Martin D. F. Wong
2012 J jnl
Advances in PCB Routing.
IPSJ Trans. Syst. LSI Des. Methodol.
Tan Yan, Qiang Ma, Martin D. F. Wong
2012 — conf
Algorithmic study on the routing reliability problem.
ISQED
Qiang Ma, Zigang Xiao, Martin D. F. Wong
2012 J jnl
Correctly Model the Diagonal Capacity in Escape Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tan Yan, Martin D. F. Wong
2012 A conf
Efficient parallel power grid analysis via Additive Schwarz Method.
ICCAD
Ting Yu, Zigang Xiao, Martin D. F. Wong
2012 — conf
Efficient pattern relocation for EUV blank defect mitigation.
ASP-DAC
Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit Onur Topaloglu
2012 — conf
Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design.
ASP-DAC
Yuelin Du, Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao
2012 — conf
Impact of lithography retargeting process on low level interconnect in 20nm technology.
SLIP
Hongbo Zhang, Yunfei Deng, Jongwook Kye, Martin D. F. Wong
2012 A conf
Layout small-angle rotation and shift for EUV defect mitigation.
ICCAD
Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Yunfei Deng, Pawitter Mangat
2012 J jnl
NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qiang Ma, Martin D. F. Wong
2012 — conf
On simulated annealing in EDA.
ISPD
Martin D. F. Wong
2012 A conf
PGT_SOLVER: An efficient solver for power grid transient analysis.
ICCAD
Ting Yu, Martin D. F. Wong
2012 — conf
Parallel implementation of R-trees on the GPU.
ASP-DAC
Lijuan Luo, Martin D. F. Wong, Lance Leong
2012 — conf
Thermal via structural design in three-dimensional integrated circuits.
ISQED
Leslie Hwang, Kevin L. Lin, Martin D. F. Wong
2012 A* conf
Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology.
DAC
Qiang Ma, Hongbo Zhang, Martin D. F. Wong
2011 J jnl
A New Strategy for Simultaneous Escape Based on Boundary Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya
2011 — conf
A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing.
ASP-DAC
Qiang Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young
2011 A conf
Accelerating aerial image simulation with GPU.
ICCAD
Hongbo Zhang, Tan Yan, Martin D. F. Wong, Sanjay J. Patel
2011 A* conf
An optimal algorithm for layer assignment of bus escape routing on PCBs.
DAC
Qiang Ma, Evangeline F. Y. Young, Martin D. F. Wong
2011 — conf
Lithography-aware layout modification considering performance impact.
ISQED
Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao
2011 — conf
Mask cost reduction with circuit performance consideration for self-aligned double patterning.
ASP-DAC
Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao
2011 — conf
Routing with graphene nanoribbons.
ASP-DAC
Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong, Deming Chen
2011 A* conf
Self-aligned double patterning decomposition for overlay minimization and hot spot detection.
DAC
Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit Onur Topaloglu
2011 J jnl
Thermal-Driven Analog Placement Considering Device Matching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang
2010 J jnl
A Routing Approach to Reduce Glitches in Low Power FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Quang Dinh, Deming Chen, Martin D. F. Wong
2010 — conf
A negotiated congestion based router for simultaneous escape routing.
ISQED
Qiang Ma, Tan Yan, Martin D. F. Wong
2010 — conf
Advances in PCB routing.
SLIP
Martin D. F. Wong
2010 A* conf
An effective GPU implementation of breadth-first search.
DAC
Lijuan Luo, Martin D. F. Wong, Wen-mei W. Hwu
2010 A* conf
An optimal algorithm for finding disjoint rectangles and its application to PCB routing.
DAC
Hui Kong, Qiang Ma, Tan Yan, Martin D. F. Wong
2010 — conf
B-escape: a simultaneous escape routing algorithm based on boundary routing.
ISPD
Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya
2010 C conf
BDD-based circuit restructuring for reducing dynamic power.
ICCD
Quang Dinh, Deming Chen, Martin D. F. Wong
2010 — conf
Configurable multi-product floorplanning.
ASP-DAC
Qiang Ma, Martin D. F. Wong, Kai-Yuan Chao
2010 — conf
Dynamic power estimation for deep submicron circuits with process variation.
ASP-DAC
Quang Dinh, Deming Chen, Martin D. F. Wong
2010 — conf
Fast block-iterative domain decomposition algorithm for IR drop analysis in large power grid.
ISQED
Yu Zhong, Martin D. F. Wong
2010 — conf
On process-aware 1-D standard cell design.
ASP-DAC
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao
2010 A conf
On the escape routing of differential pairs.
ICCAD
Tan Yan, Pei-Ci Wu, Qiang Ma, Martin D. F. Wong
2010 — conf
Optimal simultaneous pin assignment and escape routing for dense PCBs.
ASP-DAC
Hui Kong, Tan Yan, Martin D. F. Wong
2010 A conf
Recent research development in PCB layout.
ICCAD
Tan Yan, Martin D. F. Wong
2009 A* conf
A correct network flow model for escape routing.
DAC
Tan Yan, Martin D. F. Wong
2009 — conf
A routing approach to reduce glitches in low power FPGAs.
ISPD
Quang Dinh, Deming Chen, Martin D. F. Wong
2009 J jnl
Archer: A History-Based Global Routing Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Muhammet Mustafa Ozdal, Martin D. F. Wong
2009 A* conf
Automatic bus planner for dense PCBs.
DAC
Hui Kong, Tan Yan, Martin D. F. Wong
2009 J jnl
BSG-Route: A Length-Constrained Routing Scheme for General Planar Topology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tan Yan, Martin D. F. Wong
2009 A* conf
Flip-chip routing with unified area-I/O pad assignments for package-board co-design.
DAC
Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang
2009 J jnl
Incremental Improvement of Voltage Assignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Huaizhi Wu, Martin D. F. Wong
2009 — conf
On using SAT to ordered escape problems.
ASP-DAC
Lijuan Luo, Martin D. F. Wong
2009 A conf
Optimal layer assignment for escape routing of buses.
ICCAD
Tan Yan, Hui Kong, Martin D. F. Wong
2009 J jnl
Theories and algorithms on single-detour routing for untangling twisted bus.
ACM Trans. Design Autom. Electr. Syst.
Tan Yan, Martin D. F. Wong
2009 A* conf
Thermal-driven analog placement considering device matching.
DAC
Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang
2009 — conf
Wire shaping is practical.
ISPD
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng
2008 J jnl
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.
ACM Trans. Design Autom. Electr. Syst.
Lei Cheng, Deming Chen, Martin D. F. Wong
2008 A conf
BSG-Route: a length-matching router for general topology.
ICCAD
Tan Yan, Martin D. F. Wong
2008 — ch.
Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach.
Encyclopedia of Algorithms
Hannah Honghua Yang, Martin D. F. Wong
2008 J jnl
DDBDD: Delay-Driven BDD Synthesis for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lei Cheng, Deming Chen, Martin D. F. Wong
2008 A conf
Efficient ASIP design for configurable processors with fine-grained resource sharing.
FPGA
Quang Dinh, Deming Chen, Martin D. F. Wong
2008 J jnl
Fast Dummy-Fill Density Analysis With Coupling Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
2008 — ch.
Global Routing Formulation and Maze Routing.
Handbook of Algorithms for Physical Design Automation
Muhammet Mustafa Ozdal, Martin D. F. Wong
2008 J jnl
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
2008 J jnl
Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules.
ACM Trans. Design Autom. Electr. Syst.
Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger
2008 — conf
Ordered escape routing based on Boolean satisfiability.
ASP-DAC
Lijuan Luo, Martin D. F. Wong
2008 J jnl
Postplacement voltage assignment under performance constraints.
ACM Trans. Design Autom. Electr. Syst.
Huaizhi Wu, Martin D. F. Wong, Wilsin Gosti
2008 J jnl
Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger
2008 — ch.
Slicing Floorplans.
Handbook of Algorithms for Physical Design Automation
Ting-Chi Wang, Martin D. F. Wong
2008 — conf
Thermal-Aware IR Drop Analysis in Large Power Grid.
ISQED
Yu Zhong, Martin D. F. Wong
2007 A conf
Archer: a history-driven global routing algorithm.
ICCAD
Muhammet Mustafa Ozdal, Martin D. F. Wong
2007 — conf
Coupling-aware Dummy Metal Insertion for Lithography.
ASP-DAC
Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang
2007 A* conf
DDBDD: Delay-Driven BDD Synthesis for FPGAs.
DAC
Lei Cheng, Deming Chen, Martin D. F. Wong
2007 — conf
Dummy fill density analysis with coupling constraints.
ISPD
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
2007 — conf
Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid.
ASP-DAC
Yu Zhong, Martin D. F. Wong
2007 — conf
Fast Placement Optimization of Power Supply Pads.
ASP-DAC
Yu Zhong, Martin D. F. Wong
2007 — conf
Fast and Accurate OPC for Standard-Cell Layouts.
ASP-DAC
David M. Pawlowski, Liang Deng, Martin D. F. Wong
2007 A* conf
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches.
DAC
Lei Cheng, Deming Chen, Martin D. F. Wong
2007 A* conf
Improving Voltage Assignment by Outlier Detection and Incremental Placement.
DAC
Huaizhi Wu, Martin D. F. Wong
2007 — conf
Is your layout density verification exact?: a fast exact algorithm for density calculation.
ISPD
Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
2007 — conf
OPC-Friendly Bus Driven Floorplanning.
ISQED
Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong
2007 A conf
Optimal bus sequencing for escape routing in dense PCBs.
ICCAD
Hui Kong, Tan Yan, Martin D. F. Wong, Muhammet Mustafa Ozdal
2007 J jnl
Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Huaizhi Wu, Martin D. F. Wong, I-Min Liu, Yusu Wang
2007 A conf
Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.
ICCAD
Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig
2007 A conf
Untangling twisted nets for bus routing.
ICCAD
Tan Yan, Martin D. F. Wong
2006 J jnl
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Muhammet Mustafa Ozdal, Martin D. F. Wong
2006 A* conf
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.
DAC
Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong
2006 J jnl
Algorithmic study of single-layer bus routing for high-speed boards.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Muhammet Mustafa Ozdal, Martin D. F. Wong
2006 J jnl
Algorithms for simultaneous escape routing and Layer assignment of dense PCBs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Muhammet Mustafa Ozdal, Martin D. F. Wong
2006 J jnl
An ECO routing algorithm for eliminating coupling-capacitance violations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
2006 — conf
An exact algorithm for the statistical shortest path problem.
ASP-DAC
Liang Deng, Martin D. F. Wong
2006 — conf
Closed form solution for optimal buffer sizing using the Weierstrass elliptic function.
ASP-DAC
Sebastian Vogel, Martin D. F. Wong
2006 J jnl
Floorplan Design for Multimillion Gate FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lei Cheng, Martin D. F. Wong
2006 J jnl
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong
2006 J jnl
Minimizing wire length in floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
2006 J jnl
Temperature-Aware Placement for SOCs.
Proc. IEEE
Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar
2006 A* conf
Timing-constrained and voltage-island-aware voltage assignment.
DAC
Huaizhi Wu, Martin D. F. Wong, I-Min Liu
2006 J jnl
Two-layer bus routing for high-speed printed circuit boards.
ACM Trans. Design Autom. Electr. Syst.
Muhammet Mustafa Ozdal, Martin D. F. Wong
2005 J jnl
An algorithm for integrated pin assignment and buffer planning.
ACM Trans. Design Autom. Electr. Syst.
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
2005 A conf
An escape routing framework for dense boards with high-speed design constraints.
ICCAD
Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger
2005 A conf
Buffer insertion under process variations for delay minimization.
ICCAD
Liang Deng, Martin D. F. Wong
2005 — conf
CMP aware shuttle mask floorplanning.
ASP-DAC
Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong
2005 — conf
Crowdedness-balanced multilevel partitioning for uniform resource utilization.
ASP-DAC
Yongseok Cheon, Martin D. F. Wong
2005 — conf
Current Calculation on VLSI Signal Interconnects.
ISQED
Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong
2005 — conf
Energy optimization in memory address bus structure for application-specific systems.
ACM Great Lakes Symposium on VLSI
Liang Deng, Martin D. F. Wong
2005 — conf
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.
ISQED
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
2005 A conf
Fast algorithms for IR drop analysis in large power grid.
ICCAD
Yu Zhong, Martin D. F. Wong
2005 — conf
Floorplanning for 3-D VLSI design.
ASP-DAC
Lei Cheng, Liang Deng, Martin D. F. Wong
2005 — conf
IR Drop and Ground Bounce Awareness Timing Model.
ISVLSI
Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong
2005 — conf
Optimal redistribution of white space for wire length minimization.
ASP-DAC
Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
2005 A conf
Optimal routing algorithms for pin clusters in high-density multichip modules.
ICCAD
Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger
2005 A conf
Post-placement voltage island generation under performance requirement.
ICCAD
Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang
2005 — conf
Redundant-via enhanced maze routing for yield improvement.
ASP-DAC
Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong
2005 J jnl
Simultaneous power supply planning and noise avoidance in floorplan design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong
2005 — conf
Wire Planning with Bounded Over-the-Block Wires.
ISQED
Hua Xiang, I-Min Liu, Martin D. F. Wong
2004 C conf
A Two-Layer Bus Routing Algorithm for High-Speed Boards.
ICCD
Muhammet Mustafa Ozdal, Martin D. F. Wong
2004 J jnl
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
2004 A conf
A provably good algorithm for high performance bus routing.
ICCAD
Muhammet Mustafa Ozdal, Martin D. F. Wong
2004 J jnl
Bus-driven floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
2004 A conf
Floorplan design for multi-million gate FPGAs.
ICCAD
Lei Cheng, Martin D. F. Wong
2004 C conf
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
ICCD
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang
2004 — conf
On handling arbitrary rectilinear shape constraint.
ASP-DAC
Xiaoping Tang, Martin D. F. Wong
2004 A* conf
Optical proximity correction (OPC): friendly maze routing.
DAC
Li-Da Huang, Martin D. F. Wong
2004 A conf
Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus.
DATE
Liang Deng, Martin D. F. Wong
2004 B conf
Rectilinear Steiner Tree Construction Using Answer Set Programming.
ICLP
Esra Erdem, Martin D. F. Wong
2004 C conf
Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers.
ICCD
Martin D. F. Wong
2004 A conf
Simultaneous escape routing and layer assignment for dense PCBs.
ICCAD
Muhammet Mustafa Ozdal, Martin D. F. Wong
2004 — conf
Tradeoff routing resource, runtime and quality in buffered routing.
ASP-DAC
Xiaoping Tang, Martin D. F. Wong
2003 A conf
A Min-Cost Flow Based Detailed Router for FPGAs.
ICCAD
Seokjin Lee, Yongseok Cheon, Martin D. F. Wong
2003 A conf
Bus-Driven Floorplanning.
ICCAD
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
2003 J jnl
Design hierarchy-guided multilevel circuit partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yongseok Cheon, Martin D. F. Wong
2003 — conf
Explicit gate delay model for timing evaluation.
ISPD
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee
2003 A conf
Length-Matching Routing for High-Speed Printed Circuit Boards.
ICCAD
Muhammet Mustafa Ozdal, Martin D. F. Wong
2003 J jnl
Maze routing with buffer insertion under transition time constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao
2003 J jnl
Min-cost flow-based algorithm for simultaneous pin assignment and routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
2003 A conf
Stable Multiway Circuit Partitioning for ECO.
ICCAD
Yongseok Cheon, Seokjin Lee, Martin D. F. Wong
2003 J jnl
Timing-driven routing for FPGAs based on Lagrangian relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seokjin Lee, Martin D. F. Wong
2002 J jnl
Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ruiqi Tian, Xiaoping Tang, Martin D. F. Wong
2002 J jnl
Maze routing with buffer insertion and wiresizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Minghorng Lai, Martin D. F. Wong
2002 J jnl
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation.
VLSI Design
Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, Martin D. F. Wong
2001 J jnl
Fast evaluation of sequence pair in block placement by longestcommon subsequence computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
2001 J jnl
Matching-based algorithm for FPGA channel segmentation design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong
2001 J jnl
Model-based dummy feature placement for oxide chemical-mechanicalpolishing manufacturability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ruiqi Tian, Martin D. F. Wong, Robert Boone
2001 J jnl
On extending slicing floorplan to handle L/T-shaped modules andabutment constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
2000 J jnl
Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Martin D. F. Wong, Dwight D. Hill
2000 J jnl
Simultaneous routing and buffer insertion with restrictions onbuffer locations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz
2000 J jnl
Slicing floorplans with range constraint.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
2000 — conf
Wire Routing and Satisfiability Planning.
Computational Logic
Esra Erdem, Vladimir Lifschitz, Martin D. F. Wong
1999 J jnl
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chris C. N. Chu, Martin D. F. Wong
1999 J jnl
An efficient and optimal algorithm for simultaneous buffer and wire sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chris C. N. Chu, Martin D. F. Wong
1999 J jnl
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong
1999 J jnl
Global routing with crosstalk constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hai Zhou, Martin D. F. Wong
1999 J jnl
Greedy wire-sizing is linear time.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chris C. N. Chu, Martin D. F. Wong
1999 J jnl
Optimal shape function for a bidirectional wire under Elmore delay model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youxin Gao, Martin D. F. Wong
1999 J jnl
Slicing floorplans with boundary constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
1999 J jnl
Wire-sizing optimization with inductance consideration using transmission-line model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youxin Gao, Martin D. F. Wong
1998 J jnl
A matrix synthesis approach to thermal placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chris C. N. Chu, Martin D. F. Wong
1998 J jnl
Network-flow-based multiway partitioning with area and pin constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Huiqun Liu, Martin D. F. Wong
1998 J jnl
Optimal min-area min-cut replication in partitioned circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hannah Honghua Yang, Martin D. F. Wong
1998 J jnl
Switch bound allocation for maximizing routability in timing-driven routing of FPGA's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kai Zhu, Martin D. F. Wong
1997 J jnl
Algorithms for an FPGA switch module routing problem with application to global routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan
1997 J jnl
Circuit clustering for delay minimization under area and pin constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hannah Honghua Yang, Martin D. F. Wong
1997 J jnl
Clock skew minimization during FPGA placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kai Zhu, Martin D. F. Wong
1997 J jnl
Minimum replication min-cut partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wai-Kei Mak, Martin D. F. Wong
1997 J jnl
Module implementation selection and its application to transistor placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
T. W. Her, Martin D. F. Wong
1997 J jnl
On optimal board-level routing for FPGA-based logic emulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wai-Kei Mak, Martin D. F. Wong
1996 J jnl
Balanced partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hannah Honghua Yang, Martin D. F. Wong
1996 J jnl
Echelon: a multilayer detailed area router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohankumar Guruswamy, Martin D. F. Wong
1996 J jnl
Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Glenn G. Lai, Donald S. Fussell, Martin D. F. Wong
1995 J jnl
On over-the-cell channel routing with cell orientations consideration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
T. W. Her, Martin D. F. Wong
1995 J jnl
Optimal net assignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong
1995 J jnl
Optimum clustering for delay minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rajmohan Rajaraman, Martin D. F. Wong
1995 J jnl
Performance-driven channel pin assignment algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
T. W. Her, Ting-Chi Wang, Martin D. F. Wong
1994 J jnl
On shifting blocks and terminals to minimize channel density.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yang Cai, Martin D. F. Wong
1993 J jnl
Efficient via shifting algorithms in channel compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yang Cai, Martin D. F. Wong
1993 J jnl
On minimizing the number of L-shaped channels in building-block layout [VLSI].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yang Cai, Martin D. F. Wong
1992 J jnl
Optimal floorplan area optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ting-Chi Wang, Martin D. F. Wong
1992 J jnl
Topological channel routing [VLSI].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell
1991 J jnl
A layout modification approach to via minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Khe-Sing The, Martin D. F. Wong, Jason Cong
1991 J jnl
Channel ordering for VLSI layout with rectilinear modules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Martin D. F. Wong, Mohankumar Guruswamy
1991 J jnl
Channel/switchbox definition for VLSI building-block layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yang Cai, Martin D. F. Wong
1991 J jnl
Optimal channel pin assignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yang Cai, Martin D. F. Wong
1988 J jnl
A new approach to three- or four-layer channel routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jason Cong, Martin D. F. Wong, C. L. Liu
1988 A conf
Channel routing order for building-block layout with rectilinear modules.
ICCAD
Mohankumar Guruswamy, Martin D. F. Wong
1988 A conf
Topological channel routing.
ICCAD
Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell
1987 — —
Algorithmic Aspects of Vlsi Circuit Layout (Channel Routing, Logic Array)
Martin D. F. Wong