Martin Clara

19 papers A 1C 1Journal 6Unranked 11
YearRankTypeTitle / Venue / Authors
2021 — conf
10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET.
ISSCC
Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Kamran Azadet
2021 — conf
10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters.
ISSCC
Martin Clara, Daniel Gruber, Albert Molina, Matteo Camponeschi, Yu-shan Wang, Christian Lindholm, Hundo Shin, Ramón Sanchez-Perez, Christoph Duller, Patrick Torta, Kamran Azadet
2021 J jnl
A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET.
IEEE J. Solid State Circuits
Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Gerhard Knoblinger, Kamran Azadet
2015 — conf
A 16-bit 10Gsps current steering RF DAC in 65nm CMOS achieving 65dBc ACLR multi-carrier performance at 4.5GHz Fout.
VLSIC
Gil Engel, Martin Clara, Haiyang Zhu, Paul Wilkins
2012 — conf
A high-input-swing common-mode-robust programmable gain amplifier in 65nm CMOS.
ESSCIRC
Daniel Gruber, Martin Clara, Berthold Seger
2011 J jnl
Jitter Noise of Sampled Multitone Signals.
IEEE Trans. Circuits Syst. II Express Briefs
Martin Clara, Nicola Da Dalt
2008 — conf
A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS.
ESSCIRC
Martin Clara, Wolfgang Klatzer, Daniel Gruber, Arnold Marak, Berthold Seger, Wolfgang Pribyl
2007 — conf
A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS.
ISSCC
Martin Clara, Wolfgang Klatzer, Berthold Seger, Antonio Di Giandomenico, Luca Gori
2007 J jnl
A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS
CoRR
Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner
2006 C conf
Clock jitter compensation for current steering DACs.
ISCAS
Andreas Wiesbauer, Dietmar Sträußnigg, Richard Gaggl, Martin Clara, Luis Hernández, Daniel Gruber
2005 J jnl
A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS.
IEEE J. Solid State Circuits
Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner
2004 A conf
A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS.
DATE
Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner
2004 — conf
A 6bit, 1.2GSps low-power flash-ADC in 0.13μm digital CMOS.
ESSCIRC
Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner
2004 J jnl
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution.
IEEE J. Solid State Circuits
Susana Patón, Antonio Di Giandomenico, Luis Hernández, Andreas Wiesbauer, Thomas Pötscher, Martin Clara
2004 — conf
Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators.
CICC
Susana Patón, Thomas Pötscher, Antonio Di Giandomenico, Klaus Kolhaupt, Luis Hernández, Andreas Wiesbauer, Martin Clara, Ramon Frutos
2004 — conf
Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13μm CMOS.
ESSCIRC
Dario Giotta, Peter Pessl, Martin Clara, Wolfgang Klatzer, Richard Gaggl
2004 — conf
Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errors.
ISCAS (1)
Martin Clara, Andreas Wiesbauer, Wolfgang Klatzer
2002 — conf
A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS.
CICC
Martin Clara, Andreas Wiesbauer, Franz Kuttner
2002 J jnl
A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS.
IEEE J. Solid State Circuits
Andreas Wiesbauer, Martin Clara, Moritz Harteneck, Thomas Pötscher, Berthold Seger, Christoph Sandner, Christian Fleischhacker