Martijn T. Bennebroek

11 papers A 1B 4Unranked 6

Year	Rank	Type	Title / Venue / Authors
2008	—	`conf`	A Novel Routing Architecture for Field-Programmable Gate-Arrays. ARCS Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki
2008	—	`conf`	Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. NOCS Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah
2007	B	`conf`	Communication-Centric SoC Debug Using Transactions. ETS Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek
2007	B	`conf`	Multiplexer-based routing fabric for reconfigurable logic. FPL Martijn T. Bennebroek, Alexander Danilin
2007	—	`conf`	Transaction-Based Communication-Centric Debug. NOCS Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek
2006	B	`conf`	Astra: An Advanced Space-Time Reconfigurable Architecture. FPL Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki
2006	—	`conf`	Energy-efficient FPGA interconnect design. DATE Designers' Forum Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek
2005	B	`conf`	A Novel Toolset for the Development of FPGA-like Reconfigurable Logic. FPL Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki
2004	A	`conf`	Low energy FPGA interconnect design. FPGA Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
2004	—	`conf`	Low energy FPGA interconnect design. ACM Great Lakes Symposium on VLSI Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
2003	—	`conf`	Validation of wire length distribution models on commercial designs. SLIP Martijn T. Bennebroek