| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2015 | C | conf |
FDL
|
| 2014 | — | conf |
ISQED
|
| 2013 | J | jnl |
IPSJ Trans. Syst. LSI Des. Methodol.
|
| 2013 | — | conf |
ASP-DAC
|
| 2013 | — | conf |
MBMV
|
| 2013 | — | conf |
MBMV
|
| 2013 | A | conf |
ICCAD
|
| 2012 | — | conf |
FDL (Selected Papers)
|
| 2012 | C | conf |
FDL
|
| 2012 | A* | conf |
DAC
|
| 2011 | — | conf |
MBMV
|
| 2011 | A* | conf |
DAC
|
| 2011 | — | conf |
MBMV
|
| 2011 | A | conf |
DATE
|
| 2010 | A* | conf |
DAC
|
| 2010 | — | conf |
MBMV
|
| 2010 | C | conf |
FDL
|
| 2010 | B | conf |
FMCAD
|
| 2009 | — | conf |
MBMV
|
| 2009 | C | conf |
FDL
|
| 2009 | — | conf |
Algorithms and Applications for Next Generation SAT Solvers
|
| 2008 | — | conf |
FDL (Selected Papers)
|
| 2008 | A* | conf |
CAV
|
| 2008 | — | conf |
MBMV
|
| 2008 | C | conf |
FDL
|
| 2008 | — | conf |
MBMV
|
| 2008 | — | conf |
SASP
|
| 2008 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2008 | — | conf |
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof.
ASP-DAC
|
| 2007 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2007 | — | conf |
MBMV
|
| 2006 | — | conf |
MBMV
|
| 2005 | A* | conf |
DAC
|
| 2005 | A | conf |
ICCAD
|
| 2004 | A | conf |
DATE
|
| 2004 | — | conf |
ASP-DAC
|
| 2004 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2003 | — | conf |
MBMV
|
| 2003 | A | conf |
DATE
|
| 2002 | — | conf |
ISVLSI
|