Markus Bühler

14 papers A 3Journal 1Unranked 10

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	Strategies for Forward Modelling of Infrared Radiative Transfer on GPUs. PARCO Paul F. Baumeister, Benedikt Rombach, Thorsten Hater, Sabine Griessbach, Lars Hoffmann, Markus Bühler, Dirk Pleiter
2016	—	`conf`	Addressing Materials Science Challenges Using GPU-accelerated POWER8 Nodes. Euro-Par Paul F. Baumeister, Marcel Bornemann, Markus Bühler, Thorsten Hater, Benjamin Krill, Dirk Pleiter, Rudolf Zeller
2016	—	`conf`	Exploring Energy Efficiency for GPU-Accelerated POWER Servers. ISC Workshops Thorsten Hater, Benedikt Anlauf, Paul F. Baumeister, Markus Bühler, Jiri Kraus, Dirk Pleiter
2016	—	`conf`	Performance of the 3D Combustion Simulation Code RECOM®-AIOLOS on IBM® POWER8® Architecture. ISC Workshops Alexander Berreth, Benedetto Risio, Markus Bühler, Benedikt Anlauf, Pascal Vezolle
2011	—	`conf`	A gate sizing method for glitch power reduction. SoCC Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz
2011	A	`conf`	A theoretical probabilistic simulation framework for dynamic power estimation. ICCAD Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz
2011	J	`jnl`	Design methodology for the IBM POWER7 microprocessor. IBM J. Res. Dev. Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez
2009	—	`conf`	Fast dynamic power estimation considering glitch filtering. SoCC Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler
2008	—	`conf`	Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl
2006	A	`conf`	DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. DATE Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp
2006	—	`conf`	Yield Improvement by Local Wiring Redundancy. ISQED Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller, Sven Peyer, Christian Schulte
1999	A	`conf`	Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach. DATE Markus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger
1998	—	`conf`	Switching Activity Analysis Using a Set Theoretical Approach. MBMV Markus Bühler, D. Dallmann, Utz G. Baitinger
1998	—	`conf`	TESA: Timeparallel Estimation of Switching Activity under a real delay model. ICECS K. Kapp, Markus Bühler, D. Dallmann, Utz G. Baitinger