Marko Aleksic

18 papers A 1B 2C 1Journal 8Unranked 6
YearRankTypeTitle / Venue / Authors
2018 — conf
Non-physical Painting Restoration in Improved Reality.
VRTCH
Marko Aleksic, Vanja Jovanovic
2015 J jnl
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits
Reza Navid, E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
2014 — conf
A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS.
ESSCIRC
Marko Aleksic
2014 — conf
A 40-Gb/s serial link transceiver in 28-nm CMOS technology.
VLSIC
E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Reza Navid, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
2010 J jnl
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.
IEEE J. Solid State Circuits
Brian S. Leibowitz, Robert Palmer, John Poulton, Yohan Frans, Simon Li, John M. Wilson, Michael Bucher, Andrew M. Fuller, John G. Eyles, Marko Aleksic, Trey Greer, Nhat Nguyen
2009 J jnl
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.
IEEE J. Solid State Circuits
Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi
2009 J jnl
Capacity of a Class of Modulo-Sum Relay Channels.
IEEE Trans. Inf. Theory
Marko Aleksic, Peyman Razaghi, Wei Yu
2008 J jnl
Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija
2007 J jnl
Capacity of a Class of Modulo-Sum Relay Channels
CoRR
Marko Aleksic, Peyman Razaghi, Wei Yu
2007 B conf
Capacity of a Class of Modulo-Sum Relay Channels.
ISIT
Marko Aleksic, Peyman Razaghi, Wei Yu
2006 J jnl
A new CFA interpolation framework.
Signal Process.
Rastislav Lukac, Konstantinos N. Plataniotis, Dimitrios Hatzinakos, Marko Aleksic
2005 — conf
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers.
PATMOS
Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija
2005 B conf
Coding for the blackwell channel: a survey propagation approach.
ISIT
Wei Yu, Marko Aleksic
2004 J jnl
A novel cost effective demosaicing approach.
IEEE Trans. Consumer Electron.
Rastislav Lukac, Konstantinos N. Plataniotis, Dimitrios Hatzinakos, Marko Aleksic
2002 — conf
Comparative analysis of double-edge versus single-edge triggered clocked storage elements.
ISCAS (5)
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2002 A conf
Conditional pre-charge techniques for power-efficient dual-edge clocking.
ISLPED
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2001 — conf
Conditional techniques for low power consumption flip-flops.
ICECS
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2001 C conf
Timing Characterization of Dual-edge Triggered Flip-flops.
ICCD
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija